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S1D13504 Color Graphics LCD/CRT Controller .D
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MSC Vertriebs-GmbH Productmarketing Displays & Systems Friedrich-Bergius-Str. 9, D - 65203 Wiesbaden Tel:+49-611-97320-0, Fax:+49-61197320-88 http://www.msc-ge.com
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Hardware Functional Specification
Document Number: X19A-A-002-19
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Copyright (c) 1997, 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
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S1D13504 X19A-A-002-19
Hardware Functional Specification Issue Date: 01/11/06
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Table of Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 1.2 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 3 4 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Overview Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Display Support Clock Source Package and Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Typical System Implementation Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Block Description 4.1 4.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Functional Block Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Display FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 LCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Power Save . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 . . . . . . . . . . . . . . . . . . . . . . . . . 18 . . . . . . . . . . . . . . . . . . . . . . . . . 19 . . . . . . . . . . . . . . . . . . . . . . . . . 20
5
Pin Out 5.1 5.2 5.3 5.4
Pinout Diagram for S1D13504F00A Pinout Diagram for S1D13504F01A Pinout Diagram for S1D13504F02A 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 LCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 CRT and External RAMDAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.5 5.6 6 7
Summary of Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Multiple Function Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
D.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 A.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1 CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1.1 SH-3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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7.1.2 7.1.3 7.1.4 7.1.5 7.2 7.3
MC68K Bus 1 Interface Timing (e.g. MC68000) . . . . . . . . . . . . . . . . . . . . . . . .38 MC68K Bus 2 Interface Timing (e.g. MC68030) . . . . . . . . . . . . . . . . . . . . . . . .40 Generic MPU Interface Synchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . .42 Generic MPU Interface Asynchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . .44
Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Memory Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.3.9 7.3.10 EDO-DRAM Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 EDO-DRAM Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 EDO-DRAM Read-Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 EDO-DRAM CAS Before RAS Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . .52 EDO-DRAM Self-Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 FPM-DRAM Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 FPM-DRAM Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 FPM-DRAM Read-Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 FPM-DRAM CAS# Before RAS# Refresh Timing . . . . . . . . . . . . . . . . . . . . . . .60 FPM-DRAM Self-Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Power-On/Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Suspend Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Single Monochrome 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Single Monochrome 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Single Color 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Single Color 8-Bit Panel Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Single Color 8-Bit Panel Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Single Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Dual Monochrome 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Dual Color 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Dual Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 16-Bit TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 CRT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 External RAMDAC Read / Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
7.4
Display Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 7.4.8 7.4.9 7.4.10 7.4.11 7.4.12 7.4.13 7.4.14
8
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8.1 8.2 Register Mapping 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.2.7 8.2.8 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Revision Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Memory Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Panel/Monitor Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Display Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Clock Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Power Save Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Look-Up Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
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8.2.9 9 9.1 9.2
External RAMDAC Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Display Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 Image Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 Half Frame Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
10 Display Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 10.1 Display Mode Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 10.2 Image Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 11 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 11.1 Maximum MCLK: PCLK Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . .118 11.2 Frame Rate Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 12 Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 12.1 Gray Shade Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 12.2 Color Display Modes 13.1 Hardware Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 13 Power Save Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 13.2 Software Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 13.3 Power Save Mode Function Summary . . . . . . . . . . . . . . . . . . . . . . . . .128 13.4 Pin States in Power Save Modes . . . . . . . . . . . . . . . . . . . . . . . . . . .128 14 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 14.1 QFP15-128 (S1D13504F00A) . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 14.2 TQFP15-128 (S1D13504F01A) . . . . . . . . . . . . . . . . . . . . . . . . . . .130 14.3 QFP20-144 (S1D13504F02A) . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 15 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 16 Sales and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
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List of Tables
Table 2-1: Table 5-1: Table 5-2: Table 5-3: Table 5-4: Table 5-5: Table 5-6: Table 5-7: Table 5-8: Table 5-9: S1D13504 Series Package list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Host Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Memory Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 LCD Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Clock Input Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 CRT and RAMDAC Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Miscellaneous Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Power Supply Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Summary of Power On / Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 5-10: Memory Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 5-11: LCD, CRT, RAMDAC Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 6-1: Table 6-2: Table 6-3: Table 6-4: Table 7-1: Table 7-2: Table 7-3: Table 7-4: Table 7-5: Table 7-6: Table 7-7: Table 7-8: Table 7-9: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Input Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Output Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 SH-3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 MC68K Bus 1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 MC68K Bus 2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Generic MPU Interface Synchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Generic MPU Interface Asynchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 EDO DRAM Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 EDO DRAM Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 EDO DRAM Read-Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 7-10: EDO-DRAM CAS Before RAS Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 7-11: EDO-DRAM Self-Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 7-12: FPM DRAM Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 7-13: FPM-DRAM Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 7-14: FPM-DRAM Read-Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 7-15: FPM-DRAM CAS# Before RAS# Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 7-16: FPM-DRAM CBR Self-Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 7-17: LCD Panel Power-On/Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 7-18: LCD Panel Suspend Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 7-19: Single Monochrome 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 7-20: Single Monochrome 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 7-21: Single Color 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 7-22: Single Color 8-Bit Panel A.C. Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 7-23: Single Color 8-Bit Panel A.C. Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 7-24: Single Color 16-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
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Table 7-25: Dual Monochrome 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Table 7-26: Dual Color 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Table 7-27: Dual Color 16-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Table 7-28: TFT A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Table 7-29: CRT A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Table 7-30: Generic Bus RAMDAC Read / Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Table 8-1: Table 8-2: Table 8-3: Table 8-4: Table 8-5: Table 8-6: Table 8-7: Table 8-8: Table 8-9: S1D13504 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 DRAM Refresh Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Panel Data Width Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 FPLINE Polarity Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 FPFRAME Polarity Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 Simultaneous Display Option Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Number of Bits-Per-Pixel Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 Pixel Panning Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 PCLK Divide Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 8-10: Suspend Refresh Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 8-11: Minimum Memory Timing Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 8-12: RAS-to-CAS Delay Timing Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 8-13: RAS Precharge Timing Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 8-14: Optimal NRC, NRP, and NRCD Values at Maximum MCLK Frequency . . . . . . . . . . . . . 109 Table 8-15: RGB Index Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 9-1: S1D13504 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Table 11-1: Maximum PCLK Frequency with EDO-DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 11-2: Maximum PCLK Frequency with FPM-DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 11-3: Example Frame Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 12-1: Look-Up Table Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 13-1: Power Save Mode Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Table 13-2: Pin States in Power Save Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
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List of Figures
Figure 3-1: Figure 3-2: Figure 3-3: Figure 3-4: Figure 4-1: Figure 5-1: Figure 5-2: Figure 5-3: Figure 7-1: Figure 7-2: Figure 7-3: Figure 7-4: Figure 7-5: Figure 7-6: Figure 7-7: Figure 7-8: Figure 7-9: Typical System Diagram - SH-3 Bus, 1Mx16 FPM/EDO-DRAM . . . . . . . . . . . . . . . . . 14 Typical System Diagram - MC68K Bus 1, 1Mx16 FPM/EDO-DRAM (16-Bit MC68000) . . . . 14 Typical System Diagram - MC68K Bus 2, 256Kx16 FPM/EDO-DRAM (32-Bit MC68030) . . 15 Typical System Diagram - Generic Bus, 1Mx16 FPM/EDO-DRAM . . . . . . . . . . . . . . . 15 System Block Diagram Showing Datapaths . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Pinout Diagram of F00A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Pinout Diagram of F01A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Pinout Diagram of F02A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SH-3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 MC68K Bus 1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 MC68K Bus 2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Generic MPU Interface Synchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Generic MPU Interface Asynchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 EDO-DRAM Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 EDO-DRAM Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 EDO-DRAM Read-Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 7-10: EDO-DRAM CAS Before RAS Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 7-11: EDO-DRAM Self-Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 7-12: FPM-DRAM Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 7-13: FPM-DRAM Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 7-14: FPM-DRAM Read-Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 7-15: FPM-DRAM CAS# Before RAS# Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 7-16: FPM-DRAM CBR Self-Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 7-17: LCD Panel Power-On/Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 7-18: LCD Panel Suspend Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 7-19: Single Monochrome 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 7-20: Single Monochrome 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 7-21: Single Monochrome 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 7-22: Single Monochrome 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 7-23: Single Color 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 7-24: Single Color 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 7-25: Single Color 8-Bit Panel Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 7-26: Single Color 8-Bit Panel A.C. Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 7-27: Single Color 8-Bit Panel Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 7-28: Single Color 8-Bit Panel A.C. Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 7-29: Single Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 7-30: Single Color 16-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 7-31: Dual Monochrome 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 7-32: Dual Monochrome 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
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Figure 7-33: Dual Color 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure 7-34: Dual Color 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figure 7-35: Dual Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Figure 7-36: Dual Color 16-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 7-37: 16-Bit TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Figure 7-38: TFT A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 7-39: CRT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 7-40: CRT A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 7-41: Generic Bus RAMDAC Read / Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Figure 9-1: Display Buffer Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Figure 10-1: 1/2/4/8 Bit-Per-Pixel Format Memory Organization . . . . . . . . . . . . . . . . . . . . . . . 115 Figure 10-2: 15/16 Bit-Per-Pixel Format Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . 116 Figure 10-3: Image Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Figure 12-1: 1 Bit-Per-Pixel - 2-Level Gray-Shade Mode Look-Up Table Architecture . . . . . . . . . . . . 121 Figure 12-2: 2 Bit-Per-Pixel - 4-Level Gray-Shade Mode Look-Up Table Architecture . . . . . . . . . . . . 122 Figure 12-3: 4 Bit-Per-Pixel - 16-Level Gray-Shade Mode Look-Up Table Architecture . . . . . . . . . . . 122 Figure 12-4: 1 Bit-Per-Pixel - 2-Level Color Look-Up Table Architecture . . . . . . . . . . . . . . . . . . 123 Figure 12-5: 2 Bit-Per-Pixel - 4-Level Color Mode Look-Up Table Architecture . . . . . . . . . . . . . . . 124 Figure 12-6: 4 Bit-Per-Pixel - 16-Level Color Mode Look-Up Table Architecture . . . . . . . . . . . . . . 125 Figure 12-7: 8 Bit-Per-Pixel - 256-Level Color Mode Look-Up Table Architecture . . . . . . . . . . . . . . 126 Figure 14-1: Mechanical Drawing QFP15-128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Figure 14-2: Mechanical Drawing TQFP15-128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Figure 14-3: Mechanical Drawing QFP20-144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
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1 Introduction
1.1 Scope
This is the Hardware Functional Specification for the S1D13504 Series Color Graphics LCD/CRT Controller Chip. Included in this document are timing diagrams, AC and DC characteristics, register descriptions, and power management descriptions. This document is intended for two audiences: Video Subsystem Designers and Software Developers. This document is updated as appropriate. Please check for the latest revision of this document before beginning any development. The latest revision can be downloaded at www.erd.epson.com. We appreciate your comments on our documentation. Please contact us via email at documentation@erd.epson.com.
1.2 Overview Description
The S1D13504 is a low cost, low power color/monochrome LCD/CRT controller interfacing to a wide range of CPUs and LCDs. The S1D13504 architecture is designed to meet the requirements of embedded markets such as Office Automation equipment, Mobile Communications devices and Hand-Held PCs where Windows CE may serve as a primary operating system. The S1D13504 supports LCD interfaces with data widths up to 16 bits. Using Frame Rate Modulation (FRM), it can display 16 shades of gray on monochrome LCD panels, up to 4096 colors on passive color LCDs, and 64K colors on active matrix TFT LCD panels. CRT support is handled through the use of an external RAMDAC interface allowing simultaneous display of both the CRT and LCD panel. A 16-bit memory interface supports up to 2M bytes of FPM-DRAM or EDODRAM. Flexible operating voltages from 2.7V to 5.5V provide for very low power consumption.
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2 Features
2.1 Memory Interface
* 16-bit DRAM interface: * EDO-DRAM up to 40MHz data rate (80M bytes per second). * FPM-DRAM up to 25MHz data rate (50M bytes per second). * Memory size options: * 512K bytes using one 256Kx16 device. * 2M bytes using one 1Mx16 device. * A configuration register can be programmed to enhance performance by tailoring the memory control output timing to the DRAM device.
2.2 CPU Interface
* Supports the following interfaces: * 8/16-bit Hitachi SH-3 bus interface. * 16-bit interface to 16/32-bit Motorola MC68K microprocessors/microcontrollers. * Philips MIPS PR31500 / PR31700. * NEC MIPS VR4102. * 8/16-bit generic interface bus. * One-Stage write buffer for minimum wait-state CPU writes. * Registers are memory-mapped; M/R# pin selects between memory and register address space. * The complete 2M byte display buffer address space is directly and contiguously available through the 21-bit address bus.
2.3 Display Support
* 4/8-bit monochrome or 4/8/16-bit color passive LCD interface for single-panel, single-drive displays. * 8-bit monochrome or 8/16-bit color passive LCD interface for dual-panel, dual-drive displays. * Direct support for 9/12-bit TFT, 18/24-bit TFT are supported up to 64K color depth (16-bit data). * External RAMDAC support using the upper byte of the LCD data bus for the RAMDAC pixel data bus. * Simultaneous display of CRT and 4/8-bit passive panel or 9-bit TFT panel: * Normal mode for cases where LCD and CRT image sizes are identical. * Line-Doubling mode for simultaneous display of 240-line images on 240-line LCD and 480line CRT. * Even-Scan and interlace modes for simultaneous display of 480-line images on 240-line LCD and 480-line CRT.
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2.4 Display Modes
* 1/2/4/8/16 bit-per-pixel modes supported on LCD. * 1/2/4/8 bit-per-pixel modes supported on CRT. * Up to 16 shades of gray by FRM on monochrome passive LCD panels; a 16x4 Look-Up Table is used to map 1/2/4 bit-per-pixel modes into these shades. * Up to 4096 colors on color passive LCD panels; three 16x4 Look-Up Tables are used to map 1/2/4/8 bit-per-pixel modes into these colors, 16 bit-per-pixel mode is mapped directly using the 4 most significant bits of the red, green and blue colors. * Up to 64K colors in 16 bit-per-pixel mode on TFT panels. * Split screen mode - allows two different images to be simultaneously displayed. * Virtual display mode - displays images larger than the panel size through the use of panning and scrolling. * Double buffering / multi-pages - for smooth animation and instantaneous screen update. * Fast-Update feature - accelerates screen update by allocating full display buffer bandwidth to CPU (see REG[23h] bit 7).
2.5 Clock Source
* Single clock input for both pixel and memory clocks. * Memory clock can be input clock or (input clock)/2 - this provides flexibility to use CPU bus clock as input clock. * Pixel clock can be memory clock, (memory clock)/2, (memory clock)/3 or (memory clock)/4.
2.6 Miscellaneous
* The memory data bus MD[15:0], is used to configure the chip at power-on. * Up to 12 General Purpose Input/Output pins are available: * GPIO0 is always available. * GPIO[3:1] are available if upper Memory Address pins are not required for DRAM support. * GPIO[11:4] are available if there is no external RAMDAC. * Suspend power save mode is initiated by hardware or software. * The SUSPEND# pin is used either as an input to initiate Suspend mode, or as a General Purpose Output that can be used to control the LCD backlight - its power-on polarity is selected by an MD configuration pin.
2.7 Package and Pin
Table 2-1: S1D13504 Series Package list Name S1D13504F00A S1D13504F01A S1D13504F02A Package QFP15 TQFP15 QFP20 Pin 128 128 144
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3 Typical System Implementation Diagrams
Power Management SH-3 BUS
SUSPEND# A21 M/R# CLKI
Oscillator
CSn# A[20:0] D[15:0]
CS# AB[20:0] DB[15:0]
FPDAT[15:8] FPDAT[7:0] FPSHIFT
UD[7:0] LD[7:0] FPSHIFT
WE1# BS# RD/WR# RD# WE0# WAIT#
4/8/16-bit LCD Display
WE1# BS# RD/WR# RD# WE0# WAIT#
S1D13504
FPFRAME FPLINE DRDY
FPFRAME FPLINE MOD
LCDPWR WE# RAS# BUSCLK RESET# LCAS# LCAS# CLKI UCAS# UCAS# CKIO RESET# MA[11:0] A[11:0] MD[15:0] D[15:0]
1Mx16 FPM/EDO-DRAM
Figure 3-1: Typical System Diagram - SH-3 Bus, 1Mx16 FPM/EDO-DRAM
.
Power Management MC68000 BUS
A[23:21] FC0, FC1 Decoder M/R# SUSPEND#
Oscillator
Decoder A[20:1] D[15:0]
CS# AB[20:1] DB[15:0]
RAS#
WE#
FPDAT[15:8] FPDAT[7:0] FPSHIFT
UD[7:0] LD[7:0] FPSHIFT
4/8/16-bit LCD Display
LDS# UDS# AS# R/W# DTACK#
AB0# WE1# BS# RD/WR# WAIT#
S1D13504
FPFRAME FPLINE DRDY
FPFRAME FPLINE MOD
LCDPWR WE# RAS# BUSCLK RESET# LCAS# LCAS# UCAS# UCAS# BCLK RESET# MA[11:0] A[11:0] MD[15:0] D[15:0]
1Mx16 FPM/EDO-DRAM
Figure 3-2: Typical System Diagram - MC68K Bus 1, 1Mx16 FPM/EDO-DRAM (16-Bit MC68000)
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RAS#
WE#
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Power Management MC68030 BUS
SUSPEND# A[31:21] FC0, FC1 Decoder M/R#
Oscillator
Decoder A[20:0] D[31:16]
CS# AB[20:0] DB[15:0]
CLKI
FPDAT[15:8] FPDAT[7:0] FPSHIFT
UD[7:0] LD[7:0] FPSHIFT
DS# AS# R/W# SIZ1 SIZ0 DSACK1#
4/8/16-bit LCD Display
WE1# BS# RD/WR# RD# WE0# WAIT#
S1D13504
FPFRAME FPLINE DRDY
FPFRAME FPLINE MOD
LCDPWR MA[8:0] WE# RAS# BUSCLK RESET# LCAS# LCAS# CLKI UCAS# UCAS# BCLK RESET# MD[15:0] D[15:0]
256Kx16 FPM/EDO-DRAM
Figure 3-3: Typical System Diagram - MC68K Bus 2, 256Kx16 FPM/EDO-DRAM (32-Bit MC68030)
.
Power Management GENERIC BUS
A21 M/R# SUSPEND#
A[8:0]
Oscillator
CSn# A[20:0] D[15:0]
CS# AB[20:0] DB[15:0]
RAS#
WE#
FPDAT[15:8] FPDAT[7:0] FPSHIFT
UD[7:0] LD[7:0] FPSHIFT
4/8/16-bit LCD Display
WE0# WE1# RD0# RD1# WAIT#
WE0# WE1# RD# RD/WR# WAIT#
S1D13504
FPFRAME FPLINE DRDY
FPFRAME FPLINE MOD
LCDPWR LCAS# LCAS# WE# RAS# BUSCLK RESET# UCAS# UCAS# BCLK RESET# MA[11:0] A[11:0] MD[15:0] D[15:0]
1Mx16 FPM/EDO-DRAM
Figure 3-4: Typical System Diagram - Generic Bus, 1Mx16 FPM/EDO-DRAM
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RAS#
WE#
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4 Block Description
4.1 Functional Block Diagram
16-bit FPM/EDO DRAM
Register
Memory Controller
Power Save
Clocks CPU R/W Host CPU / MPU I/F Display FIFO Look-Up Table LCD I/F
LCD DAC Data
DAC Control CRTC Bus Clock Memory Clock Pixel Clock
Figure 4-1: System Block Diagram Showing Datapaths
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4.2 Functional Block Descriptions 4.2.1 Host Interface
The Host Interface block provides the means for the CPU/MPU to communicate with the display buffer and internal registers, via one of the supported bus interfaces.
4.2.2 Memory Controller
The Memory Controller block arbitrates between CPU accesses and display refresh accesses as well as generates the necessary signals to interface to one of the supported 16-bit memory devices (FPMDRAM or EDO-DRAM).
4.2.3 Display FIFO
The Display FIFO block fetches display data from the Memory Controller for display refresh.
4.2.4 Look-Up Table
The Look-Up Table block contains three 16x4 Look-Up Tables, one for each primary color. In monochrome mode only one of these Look-Up Tables is selected and used.
4.2.5 LCD Interface
The LCD Interface block performs frame rate modulation for passive LCD panels. It also generates the correct data format and timing control signals for various LCD and TFT panels.
4.2.6 Power Save
The Power Save block contains the power save mode circuitry.
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5 Pin Out
5.1 Pinout Diagram for S1D13504F00A
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VSS FPDAT15 FPDAT14 FPDAT13 FPDAT12 FPDAT11 FPDAT10 FPDAT9 FPDAT8 VSS DACCLK BLANK# DACRD# IOVDD FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT2 FPDAT1 FPDAT0 VSS FPSHIFT DRDY LCDPWR FPLINE FPFRAME VSS MD15 MD0 MD14 FPDAT3
97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
COREVDD DACP0 DACWR# DACRS0 DACRS1 HRTC VRTC VSS CLKI SUSPEND# TESTEN BUSCLK VSS IOVDD AB20 AB19 AB18 AB17 AB16 AB15 AB14 AB13 AB12 AB11 AB10 AB9 AB8 AB7 AB6 AB5 AB4 AB3 RD/WR# RESET# WAIT# IOVDD GPIO0 WE0# WE1# DB15 DB14 DB13 DB12 DB11 DB10 M/R# VSS
MD1 MD13 MD2 MD12 MD3 MD11 MD4 MD10 MD5 MD9 MD6 MD8 MD7 VSS LCAS# UCAS# WE# RAS# IOVDD MA9 MA11 MA8 MA10 MA7 MA0 MA6 MA1 MA5 MA2 MA4 MA3 COREVDD VSS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
S1D13504F00A
AB1 2
BS#
DB8
DB5
DB4
DB3
DB2
DB1
DB0
DB6 DB7
DB9
Package type: 128 pin surface mount QFP15
AB2 1
AB0 3
CS# 4
RD# 6 7
5
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 5-1: Pinout Diagram of F00A
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5.2 Pinout Diagram for S1D13504F01A
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VSS FPDAT15 FPDAT14 FPDAT13 FPDAT12 FPDAT11 FPDAT10 FPDAT9 FPDAT8 VSS DACCLK BLANK# DACRD# IOVDD FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT2 FPDAT1 FPDAT0 VSS FPSHIFT DRDY LCDPWR FPLINE FPFRAME VSS MD15 MD0 MD14 FPDAT3
97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
COREVDD DACP0 DACWR# DACRS0 DACRS1 HRTC VRTC VSS CLKI SUSPEND# TESTEN BUSCLK VSS IOVDD AB20 AB19 AB18 AB17 AB16 AB15 AB14 AB13 AB12 AB11 AB10 AB9 AB8 AB7 AB6 AB5 AB4 AB3 RD/WR# RESET# WAIT# IOVDD GPIO0 WE0# WE1# DB15 DB14 DB13 DB12 DB11 DB10 M/R# VSS
MD1 MD13 MD2 MD12 MD3 MD11 MD4 MD10 MD5 MD9 MD6 MD8 MD7 VSS LCAS# UCAS# WE# RAS# IOVDD MA9 MA11 MA8 MA10 MA7 MA0 MA6 MA1 MA5 MA2 MA4 MA3 COREVDD VSS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
S1D13504F01A
AB1 2
BS#
DB8
DB5
DB4
DB3
DB2
DB1
DB0
DB6 DB7
DB9
Package type: 128 pin surface mount TQFP15
Hardware Functional Specification Issue Date: 01/11/06
AB2 1
AB0 3
CS# 4
RD# 6 7
5
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 5-2: Pinout Diagram of F01A
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5.3 Pinout Diagram for S1D13504F02A
108107 10610510410310210110099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
FPDAT3 NC NC FPDAT13 FPDAT12 FPDAT11 FPDAT10 FPDAT9 FPDAT8 VSS DACCLK BLANK# DACRD# IOVDD FPDAT7 FPDAT6 FPDAT5 FPDAT1 FPDAT0 MD0 NC NC VSS FPDAT15 FPDAT14 FPDAT4 FPDAT2 VSS FPSHIFT DRDY LCDPWR FPLINE FPFRAME VSS MD15 MD14
109 NC 110
NC COREVDD
111
NC NC MD1 MD13 MD2 MD12 MD3 MD11 MD4 MD10 MD5 MD9 MD6 MD8 MD7 VSS LCAS# UCAS# WE# RAS# IOVDD MA9 MA11 MA8 MA10 MA7 MA0 MA6 MA1 MA5 MA2 MA4 MA3 COREVDD NC NC
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
112 DACP0 113 114
DACWR# DACRS0 HRTC VRTC VSS
115 DACRS1 116 117 118
119 CLKI 120 121 122
SUSPEND# TESTEN BUSCLK IOVDD AB20 AB19 AB17 AB16 AB14
123 VSS 124 125 126
127 AB18 128 129 130 AB15 131 132 AB13 133 134 AB11 135
AB10 AB9 AB8 AB12
S1D13504F02A
136 137
138 AB7 139 AB6 140 141
AB5 AB4
142 AB3 143 NC 144 NC
RD/WR# RESET# IOVDD WAIT# GPIO0 WE0# WE1# DB11 DB10 DB15 DB14 DB13 DB12 M/R#
NC VSS
VSS
RD#
DB9
DB6 DB7
DB8
DB5
DB4
DB3
DB2
DB1
DB0
CS#
AB2
BS#
AB1
AB0
Package type: 144 pin surface mount QFP20
NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
NC
NC
Figure 5-3: Pinout Diagram of F02A
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5.4 Pin Description
Key:
I O IO P C CD CS COx TSx TSxD CNx = = = = = = = = = = = Input Output Bi-Directional (Input/Output) Power pin CMOS level input CMOS level input with pull-down resistor (typical values of 100K/180K at 5V/3.3V respectively) CMOS level Schmitt input CMOS output driver, x denotes driver type (1=3/-1.5mA, 2=6/-3mA, 3=12/-6mA) Tri-state CMOS output driver, x denotes driver type (1=3/-1.5mA, 2=6/-3mA, 3=12/-6mA) Tri-state CMOS output driver with pull-down resistor (typical values of 100K/180K at 5V/3.3V respectively), x denotes driver type (1=3/-1.5mA, 2=6/-3mA, 3=12/-6mA) CMOS low-noise output driver, x denotes driver type (1=3/-1.5mA, 2=6/-3mA, 3=12/-6mA)
5.4.1 Host Interface
Table 5-1: Host Interface Pin Descriptions Pin Name Type Pin # F00A F02A F01A Driver Reset = 0 Value Description This pin has multiple functions. * * * * For SH-3 mode, this pin inputs system address bit 0 (A0). For MC68K Bus 1, this pin inputs the lower data strobe (LDS#). For MC68K Bus 2, this pin inputs system address bit 0 (A0). For Generic Bus, this pin inputs system address bit 0 (A0).
AB0
I
3
5
CS
Hi-Z
See Table 5-9: "Host Bus Interface Pin Mapping," on page 31 for summary. AB[20:1] I 111-128 125-142 C 1, 2 3,4 Hi-Z System address bus bits [20:1]. System data bus. Unused data pins should be connected to IO VDD. * For SH-3 mode, these pins are connected to D[15:0]. * For MC68K Bus 1, these pins are connected to D[15:0]. * For MC68K Bus 2, these pins are connected to D[31:16] for 32bit devices (e.g. MC68030) or D[15:0] for 16-bit devices (e.g. MC68340). * For Generic Bus, these pins are connected to D[15:0]. See Table 5-9: "Host Bus Interface Pin Mapping," on page 31 for summary.
DB[15:0]
IO
16-31
18-33
C/TS2
Hi-Z
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Table 5-1: Host Interface Pin Descriptions (Continued) Pin Name Type Pin # F00A F02A F01A Driver Reset = 0 Value Description This pin has multiple functions. * For SH-3 mode, this pin inputs the write enable signal for the upper data byte (WE1#). * For MC68K Bus 1, this pin inputs the upper data strobe (UDS#). * For MC68K Bus 2, this pin inputs the data strobe (DS#). * For Generic Bus, this pin inputs the write enable signal for the upper data byte (WE1#). See Table 5-9: "Host Bus Interface Pin Mapping," on page 31. This input pin is used to select between the memory and register address spaces of the S1D13504. M/R# is set high to access the memory and low to access the registers. See Section 8.1, "Register Mapping" on page 89. See Table 5-9: "Host Bus Interface Pin Mapping," on page 31. CS# BUSCLK I I 4 108 6 122 C C Hi-Z Hi-Z Chip select input. See Table 5-9: "Host Bus Interface Pin Mapping," on page 31. System bus clock. See Table 5-9: "Host Bus Interface Pin Mapping," on page 31. This pin has multiple functions. * * * * For SH-3 mode, this pin inputs the bus start signal (BS#). For MC68K Bus 1, this pin inputs the address strobe (AS#). For MC68K Bus 2, this pin inputs the address strobe (AS#). For Generic Bus, this pin must be tied to IO VDD.
WE1#
I
9
11
CS
Hi-Z
M/R#
I
5
7
C
Hi-Z
BS#
I
6
8
CS
Hi-Z
See Table 5-9: "Host Bus Interface Pin Mapping," on page 31. This pin has multiple functions. * For SH-3 mode, this pin inputs the RD/WR# signal. The S1D13504 needs this signal for early decode of the bus cycle. * For MC68K Bus 1, this pin inputs the R/W# signal. * For MC68K Bus 2, this pin inputs the R/W# signal. * For Generic Bus, this pin inputs the read command for the upper data byte (RD1#). See Table 5-9: "Host Bus Interface Pin Mapping," on page 31. This pin has multiple functions. * * * * For SH-3 mode, this pin inputs the read signal (RD#). For MC68K Bus 1, this pin must be tied to IO VDD. For MC68K Bus 2, this pin inputs the bus size bit 1 (SIZ1). For Generic Bus, this pin inputs the read command for the lower data byte (RD0#).
RD/WR#
I
10
12
CS
Hi-Z
RD#
I
7
9
CS
Hi-Z
See Table 5-9: "Host Bus Interface Pin Mapping," on page 31.
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Table 5-1: Host Interface Pin Descriptions (Continued) Pin Name Type Pin # F00A F02A F01A Driver Reset = 0 Value Description This pin has multiple functions. * For SH-3 mode, this pin inputs the write enable signal for the lower data byte (WE0#). * For MC68K Bus 1, this pin must be tied to IO VDD. * For MC68K Bus 2, this pin inputs the bus size bit 0 (SIZ0). * For Generic Bus, this pin inputs the write enable signal for the lower data byte (WE0#). See Table 5-9: "Host Bus Interface Pin Mapping," on page 31. The active polarity of the WAIT# output is configurable on the rising edge of RESET# - see Section 5.5, "Summary of Configuration Options" on page 30. This pin has multiple functions. * For SH-3 mode, this pin outputs the wait request signal (WAIT#); MD5 must be pulled low during reset by the internal pull-down resistor. * For MC68K Bus 1, this pin outputs the data transfer acknowledge signal (DTACK#); MD5 must be pulled high during reset by an external pull-up resistor. * For MC68K Bus 2, this pin outputs the data transfer and size acknowledge bit 1 (DSACK1#); MD5 must be pulled high during reset by an external pull-up resistor. * For Generic Bus, this pin outputs the wait signal (WAIT#); MD5 must be pulled low during reset by the internal pull-down resistor. See Table 5-9: "Host Bus Interface Pin Mapping," on page 31. RESET# I 11 13 CS Input 0 Active low input to clear all internal registers and to force all signals to their inactive states.
WE0#
I
8
10
CS
Hi-Z
WAIT#
O
13
15
TS2
Hi-Z
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5.4.2 Memory Interface
Table 5-2: Memory Interface Pin Descriptions Pin # Pin Name Type F00A F01A F02A Driver Reset = 0 Value Description This pin has multiple functions. * For dual CAS# DRAM, this is the column address strobe for the lower byte (LCAS#). * For single CAS# DRAM, this is the column address strobe (CAS#). See Table 5-10: "Memory Interface Pin Mapping," on page 32 for summary. This pin has multiple functions. * For dual CAS# DRAM, this is the column address strobe for the upper byte (UCAS#). * For single CAS# DRAM, this is the write enable signal for the upper byte (UWE#). See Table 5-10: "Memory Interface Pin Mapping," on page 32 for summary. This pin has multiple functions. * For dual CAS# DRAM, this is the write enable signal (WE#). * For single CAS# DRAM, this is the write enable signal for the lower byte (LWE#). See Table 5-10: "Memory Interface Pin Mapping," on page 32 for summary. RAS# O 47 67, 65, 63, 61, 59, 57, 55, 53, 52, 54, 56, 58, 60, 62, 64, 66 53 76, 70, 68, 66, 64, 62, 60, 58, 59, 61, 63, 65, 67, 69, 75, 77 CO1 Output 1 Row address strobe. These pins have multiple functions. * Bi-directional memory data bus. * During reset, these pins are inputs and their states at the rising edge of RESET# are used to configure the chip. Hi-Z CD2/TS1 Internal pull-down resistors (typical values of (pulled 0) 100K/100K/120K at 5.0V/3.3V/3.0V respectively) pull the reset states to 0. External pull-up resistors can be used to pull the reset states to 1. See Section 5.5, "Summary of Configuration Options" on page 30.
LCAS#
O
50
56
CO1
Output 1
UCAS#
O
49
55
CO1
Output 1
WE#
O
48
54
CO1
Output 1
MD[15:0] IO
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Table 5-2: Memory Interface Pin Descriptions (Continued) Pin # Pin Name Type F00A F01A 43, 41, 39, 37, 35, 34, 36, 38, 40 F02A 46, 44, 42, 40, 41, 43, 45, 47, 49 Driver Reset = 0 Value Description
MA[8:0]
O
CO1
Output 0
Multiplexed memory address.
This pin has multiple functions. * For 2M byte DRAM, this is memory address bit 9 (MA9). * For asymmetrical 512K byte DRAM, this is memory address bit 9 (MA9). Hi-Z / Output 01 * For symmetrical 512K byte DRAM, this pin can be used as general purpose IO (GPIO3). See Table 5-10: "Memory Interface Pin Mapping," on page 32 for summary. This pin has multiple functions. * For asymmetrical 2M byte DRAM, this is memory address bit 10 (MA10). Hi-Z / * For symmetrical 2M byte DRAM and all 512K byte DRAM, Output 01 this pin can be used as general purpose IO (GPIO1). See Table 5-10: "Memory Interface Pin Mapping," on page 32 for summary. This pin has multiple functions. * For asymmetrical 2M byte DRAM, this is memory address bit 11 (MA11). Hi-Z / 1 * For symmetrical 2M byte DRAM and all 512K byte DRAM, Output 0 this pin can be used as general purpose IO (GPIO2). See Table 5-10: "Memory Interface Pin Mapping," on page 32 for summary. 1 When configured as IO pins.
MA9
IO
45
51
C/TS1
MA10
IO
42
48
C/TS1
MA11
IO
44
50
C/TS1
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5.4.3 LCD Interface
Table 5-3: LCD Interface Pin Descriptions Pin # Pin Name Type F00A F!A Driver F02A Reset = 0 Value Output 0 Panel Data These pins have multiple functions. FPDAT[15:9] O 95-89 105-99 CN3 * Panel Data for 16-bit panels. Output 0 * Pixel Data for external RAMDAC support. See Table 5-11: "LCD, CRT, RAMDAC Interface Pin Mapping," on page 33. FPFRAME FPLINE FPSHIFT O O O 69 70 73 79 80 83 CN3 CN3 CN3 Output 0 Frame Pulse Output 0 Line Pulse Output 0 Shift Clock Pulse LCD power control output. The active polarity of this output is selected by the state of MD10 at the rising edge of RESET# - see Section 5.5, "Summary of Configuration Options" on page 30. This output is controlled by the power save mode circuitry see Section 13, "Power Save Modes" on page 127 for details. This pin has multiple functions which are automatically selected depending on panel type used. * For TFT panels, this is the display enable output (DRDY). * For passive LCDs with Format 1 interfaces, this is the Output 0 2nd Shift Clock (FPSHIFT2). * For all other LCD panels, this is the LCD backplane bias signal (MOD). See Table 5-11: "LCD, CRT, RAMDAC Interface Pin Mapping," on page 33 and REG[02h] for details. 1 Output may be 1 or 0. Description
FPDAT[8:0]
O
88, 82-75 98, 92-85 CN3
LCDPWR
O
71
81
CO1
Output1
DRDY
O
72
82
CN3
5.4.4 Clock Input
Table 5-4: Clock Input Pin Description Pin # Pin Name Type F00A F01A 105 F02A Driver Reset = 0 Value Description Input clock for the internal pixel clock (PCLK) and memory clock (MCLK). PCLK and MCLK are derived from CLKI - see REG[19h] for details.
CLKI
I
119
C
Hi-Z
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5.4.5 CRT and External RAMDAC Interface
Table 5-5: CRT and RAMDAC Interface Pin Descriptions Pin # Pin Name Type F00A F01A F02A Driver Reset = 0 Value Description This pin has multiple functions. DACRD# IO 84 94 C/TS1 * Read signal for external RAMDAC support. Hi-Z / * General Purpose IO (GPIO4). Output 11 See Table 5-11: "LCD, CRT, RAMDAC Interface Pin Mapping," on page 33. This pin has multiple functions. DACWR# IO 99 113 C/TS1 * Write signal for external RAMDAC support. Hi-Z / * General Purpose IO (GPIO7). Output 11 See Table 5-11: "LCD, CRT, RAMDAC Interface Pin Mapping," on page 33. This pin has multiple functions. DACRS1 IO 101 115 C/TS1 * Register Select bit 1 for external RAMDAC support. Hi-Z / * General Purpose IO (GPIO9). Output 01 See Table 5-11: "LCD, CRT, RAMDAC Interface Pin Mapping," on page 33. This pin has multiple functions. DACRS0 IO 100 114 C/TS1 * Register Select bit 0 for external RAMDAC support. Hi-Z / * General Purpose IO (GPIO8). Output 01 See Table 5-11: "LCD, CRT, RAMDAC Interface Pin Mapping," on page 33. This pin has multiple functions. DACP0 IO 98 112 C/CN3 * Pixel Data bit 0 for external RAMDAC support. Hi-Z / * General Purpose IO (GPIO6). Output 01 See Table 5-11: "LCD, CRT, RAMDAC Interface Pin Mapping," on page 33.
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Table 5-5: CRT and RAMDAC Interface Pin Descriptions (Continued) Pin # Pin Name Type F00A F01A F02A Driver Reset = 0 Value Description This pin has multiple functions. HRTC IO 102 116 C/CN3 * Horizontal Retrace signal for CRT. Hi-Z / 1 * General Purpose IO (GPIO10). Output 0 See Table 5-11: "LCD, CRT, RAMDAC Interface Pin Mapping," on page 33. This pin has multiple functions. VRTC IO 103 117 C/CN3 * Vertical Retrace signal for CRT. Hi-Z / * General Purpose IO (GPIO11). Output 01 See Table 5-11: "LCD, CRT, RAMDAC Interface Pin Mapping," on page 33. This pin has multiple functions. BLANK# IO 85 95 C/CN3 * Blanking signal for DAC. Hi-Z / 1 * General Purpose IO (GPIO5). Output 0 See Table 5-11: "LCD, CRT, RAMDAC Interface Pin Mapping," on page 33. Output 0 Pixel Clock for RAMDAC.
DACCLK 1
O
86
96
C/CN3
When configured as IO pins
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5.4.6 Miscellaneous
Table 5-6: Miscellaneous Pin Descriptions Pin # Pin Name Type F00A F01A F02A Driver Reset = 0 Value Description This pin has multiple functions. * When MD9 = 0 at rising edge of RESET#, this pin is an active-low input used to place the S1D13504 into suspend mode; see Section 13, "Power Save Modes" on page 127 for details. * When MD[10:9] = 01 at rising edge of RESET#, this pin is an output with a reset state of 0. Its state is controlled by REG[21h] bit 7. * When MD[10:9] = 11 at rising edge of RESET#, this pin is an output with a reset state of 1. Its state is controlled by REG[21h] bit 7. General Purpose IO pin 0. Test Enable. This in should be connected to VSS for normal operation.
SUSPEND# IO
106
120
CS/TS1
Hi-Z / Output1
GPIO0 TSTEN
IO I
12 107
14 121
C/TS1 CD
Hi-Z Hi-Z (pulled 0)
NC
-
-
1, 2, 3538, 7174, 107- 110, 143, 144
-
No connect
1
When configured as IO pin. Output may be 1 or 0.
5.4.7 Power Supply
Table 5-7: Power Supply Pin Descriptions Pin # Pin Name COREVDD IOVDD P P Type F00A F01A 33, 97 F02A 39, 111 P Driver Core VDD IO VDD Description
14, 46, 83, 16, 52, 93, P 110 124 15, 32, 51, 68, 74, 87, 96, 104, 109 17, 34, 57, 78, 84, 97, P 106, 118, 123,
VSS
P
Common VSS
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5.5 Summary of Configuration Options
Table 5-8: Summary of Power On / Reset Options Pin Name MD0 value on this pin at rising edge of RESET# is used to configure: 1 8-bit host bus interface 16-bit host bus interface 0 (1/0)
MD[3:1]
Select host bus interface: 000 = SH-3 bus interface 001 = MC68K bus 1 (e.g. MC68000) 010 = MC68K bus 2 (e.g. MC68030) 011 = Generic bus interface (e.g. Philips MIPS PR31500/PR31700; NEC MIPS VR4102) 1XX = reserved Little Endian WAIT# is active high (1 = insert wait state) Memory Address/GPIO configuration: 00 = symmetrical 256Kx16 DRAM. 01 = symmetrical 1Mx16 DRAM. 10 = asymmetrical 256Kx16 DRAM. 11 = asymmetrical 1Mx16 DRAM. MA[8:0] MA[9:0] MA[9:0] MA[11:0] Big Endian WAIT# is active low (0 = insert wait state) = DRAM address. MA[11:9] = DRAM address. MA[11:10] = DRAM address. MA[11:10] = DRAM address. = GPIO[2:1] and GPIO3. = GPIO[2:1]. = GPIO[2:1].
MD4 MD5
MD[7:6]
MD8 MD9 MD10 MD[15:11]
Configure DACRD#, BLANK#, DACP0, DACWR#, DACRS0, DACRS1, HRTC, VRTC as General Purpose IO (GPIO[11:4]). SUSPEND# pin configured as GPO output. Active low LCDPWR or GPO polarities. Not used.
Configure DACRD#, BLANK#, DACP0, DACWR#, DACRS0, DACRS1, HRTC, VRTC as DAC and CRT outputs. SUSPEND# pin configured as SUSPEND# input. Active high LCDPWR or GPO polarities.
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5.6 Multiple Function Pin Mapping
Table 5-9: Host Bus Interface Pin Mapping S1D13504 Pin Names AB[20:1] AB0 DB[15:0] WE1# M/R# CS# BUSCLK BS# RD/WR# RD# WE0# WAIT# RESET# SH-3 A[20:1] A0 D[15:0] WE1# External Decode CSn# CKIO BS# RD/WR# RD# WE0# WAIT# RESET# MC68K Bus 1 A[20:1] LDS# D[15:0] UDS# External Decode External Decode CLK AS# R/W# Connect to IO VDD Connect to IO VDD DTACK# RESET# MC68K Bus 2 A[20:1] A0 D[31:16] DS# External Decode External Decode CLK AS# R/W# SIZ1 SIZ0 DSACK1# RESET# Generic MPU A[20:1] A0 D[15:0] WE1# External Decode External Decode BCLK Connect to IO VDD RD1# RD0# WE0# WAIT# RESET#
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Table 5-10: Memory Interface Pin Mapping S1D13504 Pin Names MD[15:0] MA[8:0] MA9 MA10 MA11 UCAS# LCAS# WE# RAS# UCAS# LCAS# WE# UWE# CAS# LWE# GPIO31 GPIO11 GPIO21 UCAS# LCAS# WE# UWE# CAS# LWE# RAS# UCAS# LCAS# WE# UWE# CAS# LWE# UCAS# LCAS# WE# FPM/EDO-DRAM Sym 256Kx16 2-CAS# 2-WE# Asym 256Kx16 2-CAS# 2-WE# A[8:0] A9 A10 A11 UWE# CAS# LWE# DQ[15:0] Sym 1Mx16 2-CAS# 2-WE# Asym 1Mx16 2-CAS# 2-WE#
Note 1. All GPIO pins default to input on reset, and unless programmed otherwise should be connected to either VSS or IO VDD if not used.
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Table 5-11: LCD, CRT, RAMDAC Interface Pin Mapping
Monochrome Passive Panel S1D13504 Pin Names Single 4-bit FPFRAME FPLINE FPSHIFT DRDY FPDAT0 FPDAT1 FPDAT2 FPDAT3 FPDAT4 FPDAT5 FPDAT6 FPDAT7 FPDAT8 FPDAT9 FPDAT10 FPDAT11 FPDAT12 FPDAT13 FPDAT14 FPDAT15 DACRD# BLANK# DACP0 DACWR# DACRS0 DACRS1 HRTC VRTC DACCLK driven 0 driven 0 driven 0 driven 0 D0 D1 D2 D3 D0 D1 D2 D3 D4 D5 D6 D7 MOD LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 driven 0 driven 0 driven 0 driven 0 D0 D1 D2 D3 D0 D1 D2 D3 D4 D5 D6 D7 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 8-bit Dual 8-bit Single 4-bit Color Passive Panel Single
Format 1
Single
Format 2
Color TFT Panel Dual 8-bit 16-bit 9-bit 12-bit 18-bit1
CRT
8-bit
8-bit FPFRAME FPLINE FPSHIFT
Note2 Note2 Note2 MOD DRDY LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 LD4 LD5 LD6 LD7 UD4 UD5 UD6 UD7 R2 R1 R0 G2 G1 G0 B2 B1 B0 driven 0 driven 0 R3 R2 R1 G3 G2 G1 B3 B2 B1 R0 G0 R5 R4 R3 G5 G4 G3 B5 B4 B3 R2 R1 G2 G1 G0 B2 B1 Note2 Note2 Note2 Note2 Note2 Note2 Note2 Note2 Note2 Note2 DACP7 DACP6 DACP5 DACP4 DACP3 DACP2 DACP1 DACRD# BLANK# DACP0 DACWR# DACRS0 DACRS1 HRTC VRTC DACCLK LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3
FPSHIFT2 D0 D1 D2 D3 D4 D5 D6 D7
driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0
driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 GPIO43 GPIO53 GPIO63 GPIO73 GPIO83 GPIO93 GPIO103 GPIO113 driven 0
driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 B0 driven 0 driven 0
Note 1. Although 18-bit TFT panels are supported only 16 data bits (64K colors) are available - R0 and B0 are not used. 2. If no LCD is active these pins are driven low. 3. All GPIO pins default to input on reset, and unless programmed otherwise should be connected to either VSS or IO VDD if not used.
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6 D.C. Characteristics
Table 6-1: Absolute Maximum Ratings Symbol Core VDD IO VDD VIN VOUT TSTG TSOL Parameter Supply Voltage Supply Voltage Input Voltage Output Voltage Storage Temperature Solder Temperature/Time VSS - 0.3 to 4.6 VSS - 0.3 to 6.0 VSS - 0.3 to IO VDD + 0.5 VSS - 0.3 to IO VDD + 0.5 -65 to 150 260 for 10 sec. max at lead Rating V V V V C C Units
Table 6-2: Recommended Operating Conditions Symbol Core VDD IO VDD VIN TOPR Parameter Supply Voltage Supply Voltage Input Voltage Operating Temperature Condition VSS = 0 V VSS = 0 V 2.7 2.7 VSS -40 25 Min Typ 3.0/3.3 3.0/3.3/5.0 3.6 5.5 IO VDD 85 Max V V V C Units
Table 6-3: Input Specifications Symbol VIL Parameter Low Level Input Voltage CMOS inputs High Level Input Voltage CMOS inputs Positive-Going Threshold CMOS Schmitt inputs Negative-Going Threshold CMOS Schmitt inputs Condition IO VDD = 3.0 3.3 5.0 3.0 3.3 5.0 3.0 3.3 5.0 3.0 3.3 5.0 1.9 2.0 3.5 1.0 1.1 2.0 0.5 0.6 0.8 -1 2.3 2.4 4.0 1.7 1.8 3.1 1 10 VIN = VDD = 3.0 = 3.3 = 5.0 60 50 50 120 100 100 300 300 300 Min Typ 0.8 0.8 1.0 Max V V V V V V V V V V V V A pF k k k Units
IO VDD =
VIH
IO VDD =
VT+
IO VDD =
VT-
IIZ CIN HRPD
Input Leakage Current Input Pin Capacitance Pull-down Resistance
VDD = Max VIH = IO VDD VIL = VSS
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Table 6-4: Output Specifications Symbol Parameter Low Level Output Voltage Type 1 - TS1, CO1, TS1D Type 2 - TS2, CO2 Type 3 - TS3, CO3 High Level Output Voltage Type 1 - TS1, CO1, TS1D Type 2 - TS2, CO2 Type 3 - TS3, CO3 Output Leakage Current Output Pin Capacitance Bidirectional Pin Capacitance Condition IOL = 3mA IOL = 6mA IOL = 12mA IOL = -1.5 mA IOL = -3 mA IOL = -6 mA IO VDD = Max VOH = VDD VOL = VSS Min Typ Max Units
VOL
0.4
V
VOH
IO VDD - 0.4
V
IOZ COUT CBID
-1
1 10 10
A pF pF
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7 A.C. Characteristics
Conditions: IO VDD = 2.7V to 5.5V unless otherwise specified TA = -40 C to 85 C Trise and Tfall for all inputs must be 5 nsec (10% ~ 90%) CL = 50pF (Bus / MPU Interface) CL = 100pF (LCD Panel Interface) CL = 10pF (Display Buffer Interface) CL = 10pF (CRT / DAC Interface)
7.1 CPU Interface Timing 7.1.1 SH-3 Interface Timing
t1 CKIO t4 A[20:0], M/R# RD/WR# t6 BS# t8 CSn# t9 WEn# RD# t11 WAIT# t13 D[15:0](write) t15 D[15:0](read) t16 t14 t12 t10 t12 t7 t5 t2 t3
Figure 7-1: SH-3 Interface Timing
Note The SH-3 Wait State Control Register for the area in which the S1D13504 resides must be set to a non-zero value.
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Table 7-1: SH-3 Interface Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t92 t10 t111 t12 t13 t14 t15 t16 Clock period Clock pulse width high Clock pulse width low A[20:0], M/R#, RD/WR# setup to CKIO A[20:0], M/R#, RD/WR# hold from CS# BS# setup BS# hold CSn# setup Falling edge RD# to D[15:0] driven Rising edge CSn# to WAIT# tri-state Falling edge CSn# to WAIT# driven CKIO to WAIT# delay D[15:0] setup to first CKIO after BS# (write cycle) D[15:0] hold (write cycle) D[15:0] valid to WAIT# rising edge (read cycle) Rising edge RD# to D[15:0] tri-state (read cycle) Parameter Min 25 5 5 4 0 3 0 0 3 0 1 3 0 0 0 2 9 4 11 15 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1.
If the S1D13504 host interface is disabled, the timing for WAIT# driven is relative to the falling edge of CSn# or the first positive edge of CKIO after A[20:0] and M/R# become valid, whichever occurs later. If the S1D13504 host interface is disabled, the timing for D[15:0] driven is relative to the falling edge of RD# or the first positive edge of CKIO after A[20:0] and M/R# become valid, whichever occurs later.
2.
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7.1.2 MC68K Bus 1 Interface Timing (e.g. MC68000)
t1 CLK t4 A[20:1] M/R# t6 CS# t16 AS# t5 t2 t3
UDS# LDS# t7 R/W# t9 DTACK# t11 D[15:0](write) t13 D[15:0](read) t14 t15 t12 t10 t8
Figure 7-2: MC68K Bus 1 Interface Timing
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Table 7-2: MC68K Bus 1 Interface Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t91 t10 t11 t12 t132 t14 t15 t16 Clock period Clock pulse width high Clock pulse width low A[20:1], M/R# setup to first CLK where CS# = 0 AS# = 0, and either UDS#=0 or LDS# = 0 A[20:1], M/R# hold from AS# CS# hold from AS# R/W# setup to before to either UDS#=0 or LDS# = 0 R/W# hold from AS# AS# = 0 and CS# = 0 to DTACK# driven high AS# high to DTACK# high impedance D[15:0] valid to second CLK where CS# = 0 AS# = 0, and either UDS#=0 or LDS# = 0 (write cycle) D[15:0] hold from falling edge of DTACK# (write cycle) Falling edge of UDS#=0 or LDS# = 0 to D[15:0] driven (read cycle) D[15:0] valid to DTACK# falling edge (read cycle) UDS# and LDS# high to D[15:0] invalid/high impedance (read cycle) AS# high setup to CLK Parameter Min 30 5 5 4 0 0 5 0 1 1 0 0 3 0 2 3 11 5 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1.
If the S1D13504 host interface is disabled, the timing for DTACK# driven high is relative to the falling edge of AS# or the first positive edge of CLK after A[20:1] and M/R# become valid, whichever occurs later. If the S1D13504 host interface is disabled, the timing for D[15:0] driven is relative to the falling edge of UDS#/LDS# or the first positive edge of CLK after A[20:1] and M/R# become valid, whichever occurs later.
2.
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7.1.3 MC68K Bus 2 Interface Timing (e.g. MC68030)
t1 CLK t4 A[20:0] SIZ[1:0] M/R# t6 CS# t16 AS# t5 t2 t3
DS# t7 R/W# t9 DSACK1# t11 D[31:16](write) t13 D[31:16](read) t14 t15 t12 t10 t8
Figure 7-3: MC68K Bus 2 Interface Timing
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Table 7-3: MC68K Bus 2 Interface Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t91 t10 t11 t12 t132 t14 t15 t16 Clock period Clock pulse width high Clock pulse width low A[20:0], SIZ[1:0], M/R# setup to first CLK where CS# = 0 AS# = 0, and either UDS#=0 or LDS# = 0 A[20:0], SIZ[1:0], M/R# hold from AS# CS# hold from AS# R/W# setup to DS# R/W# hold from AS# AS# = 0 and CS# = 0 to DSACK1# driven high AS# high to DSACK1# high impedance D[31:16] valid to second CLK where CS# = 0 AS# = 0, and either UDS#=0 or LDS# = 0 (write cycle) D[31:16] hold from falling edge of DSACK1# (write cycle) Falling edge of UDS# = 0 or LDS# = 0 to D[31:16] driven (read cycle) D[31:16] valid to DSACK1# falling edge (read cycle) UDS# and LDS# high to D[31:16] invalid/high impedance (read cycle) AS# high setup to CLK Parameter Min 30 5 5 4 0 0 5 0 1 1 0 0 3 0 2 3 11 5 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1.
If the S1D13504 host interface is disabled, the timing for DSACK1# driven high is relative to the falling edge of AS# or the first positive edge of CLK after A[20:0] and M/R# become valid, whichever occurs later. If the S1D13504 host interface is disabled, the timing for D[15:0] driven is relative to the falling edge of UDS#/LDS# or the first positive edge of CLK after A[20:1] and M/R# becomes valid, whichever occurs later.
2.
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7.1.4 Generic MPU Interface Synchronous Timing
TBCLK BCLK t1 A[20:0] M/R# t1 CS# t3 t1 RD0#,RD1# WE0#,WE1# t4 Hi-Z WAIT# t7 Hi-Z D[15:0](write) t9 Hi-Z D[15:0](read) Valid t10 Valid t11 Hi-Z t8 Hi-Z t5 t2 t1 t2 t2 t2 Valid t1 t2 t1 t2
t6 Hi-Z
Figure 7-4: Generic MPU Interface Synchronous Timing
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Table 7-4: Generic MPU Interface Synchronous Timing Symbol TBCLK t1 t2 t3 t41 t5 t6 t7 t8 t92 t10 t11 Bus clock period A[20:0], M/R#, CS#, RD0#,RD1#,WE0#,WE1# hold time A[20:0], M/R#, CS#, RD0#,RD1#,WE0#,WE1# setup time RD0#,RD1#,WE0#,WE1# high to A[20:0], M/R# invalid and CS# high RD0#,RD1#,WE0#,WE1# low and CS# low to WAIT# driven low BCLK to WAIT# high RD0#,RD1#,WE0#,WE1# high to WAIT# high impedance D[15:0] valid to second BCLK where RD0#,RD1#,WE0#,WE1# low and CS# low (write cycle) D[15:0] hold from WE0#, WE1# high (write cycle) RD0#,RD1# low to D[15:0] driven (read cycle) D[15:0] valid to WAIT# high (read cycle) RD0#, RD1# high to D[15:0] high impedance (read cycle) Parameter Min 25 1 5 0 1 0 1 5 0 3 0 2 10 15 7 15 6 Max Units ns ns ns ns ns ns ns ns ns ns
1.
If the S1D13504 host interface is disabled, the timing for WAIT# driven low is relative to the falling edge of CS# and RD0#, RD1#, WE0#, WE1# or the first positive edge of BCLK after A[20:0] and M/R# become valid, whichever occurs later. If the S1D13504 host interface is disabled, the timing for D[15:0] driven is relative to the falling edge of RD0#, RD1# or the first positive edge of BCLK after A[20:0] and M/R# become valid, whichever occurs later.
2.
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7.1.5 Generic MPU Interface Asynchronous Timing
TBCLK BCLK
A[20:0] M/R# t1 CS# t2 RD0#,RD1# WE0#,WE1#
Valid
t3
Hi-Z WAIT#
t4
t5 Hi-Z t7 Valid Hi-Z t10 Valid Hi-Z
t6 D[15:0](write) Hi-Z t8 D[15:0](read) Hi-Z t9
Figure 7-5: Generic MPU Interface Asynchronous Timing
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Table 7-5: Generic MPU Interface Asynchronous Timing Symbol TBCLK t1 t2 t3 t41 t5 t6 t7 t82 t9 t10 Bus clock period RD0#, RD1#, WE0#, WE1# low to CS# low A[20:0], M/R# valid to RD0#, RD1#, WE0#, WE1# low RD0#, RD1#, WE0#, WE1# high to A[20:0], CS#, M/R# invalid and CS# high CS# low to WAIT# driven low RD0#, RD1#, WE0#, WE1# high to WAIT# high impedance WE0#, WE1# low to D[15:0] valid (write cycle) D[15:0] hold from WE0#, WE1# high (write cycle) RD0#, RD1# low to D[15:0] driven (read cycle) D[15:0] valid to WAIT# high (read cycle) RD0#, RD1# high to D[15:0] high impedance (read cycle) 0 3 0 2 10 15 Parameter Min 25 4 0 0 1 1 7 6 20 Max Units ns ns ns ns ns ns ns ns ns
1.
If the S1D13504 host interface is disabled, the timing for WAIT# driven low is relative to the falling edge of CS# or the first positive edge of BCLK after A[20:0] and M/R# become valid, whichever occurs later. If the S1D13504 host interface is disabled, the timing for D[15:0] driven is relative to the falling edge of RD0#, RD1# or the first positive edge of BCLK after A[20:0] and M/R# become valid, whichever occurs later.
2.
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7.2 Clock Input Requirements
Clock Input Waveform
t PWH t PWL
V IH VIL
TCLKI
Figure 7-6: Clock Input Requirements Table 7-6: Clock Input Requirements Symbol TCLKI TPCLK TMCLK tPWH tPWL Parameter Input Clock Period (CLKI) Pixel Clock Period (PCLK) not shown Memory Clock Period (MCLK) not shown Input Clock Pulse Width High (CLKI) Input Clock Pulse Width Low (CLKI) Min 12.5 25 25 45% 45% Typ Max Units ns ns ns TCLKI TCLKI
55% 55%
Note When CLKI is more than 40MHz, REG[19h] bit 2 must be set to 1 (MCLK = CLKI/2). There is no minimum frequency for CLKI.
7.3 Memory Interface Timing 7.3.1 EDO-DRAM Read Timing
t1
Memory Clock
t2 t3 t4 t5 t6 C3 t7 t8 t9
MA RAS# CAS#
R
C1
C2
C4
t10
t11 t12 t15 t13 t14 t16
MD(Read)
d1
d2
d3
d4
Figure 7-7: EDO-DRAM Read Timing
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Table 7-7: EDO DRAM Read Timing Symbol t1 t2 Memory clock period Random read or write cycle time (REG[22h] bits [6:5] = 00) Random read or write cycle time (REG[22h] bits [6:5] = 01) Random read or write cycle time (REG[22h] bits [6:5] = 10) Row address setup time (REG[22h] bits [3:2] = 00) t3 Row address setup time (REG[22h] bits [3:2] = 01) Row address setup time (REG[22h] bits [3:2] = 10) t4 t5 t6 t7 t8 t9 t10 Row address hold time (REG[22h] bits [3:2] = 00 or 10) Row address hold time (REG[22h] bits [3:2] = 01) Column address setup time Column address hold time CAS# pulse width CAS# precharge time RAS# hold time RAS# precharge time (REG[22h] bits [3:2] = 00) RAS# precharge time (REG[22h] bits [3:2] = 01) RAS# precharge time (REG[22h] bits [3:2] = 10) RAS# to CAS# delay time (REG[22h] bit 4 = 0 and bits [3:2] = 00 or 10) t11 RAS# to CAS# delay time (REG[22h] bit 4 = 1 and bits [3:2] = 00 or 10) RAS# to CAS# delay time (REG[22h] bits [3:2] = 01) Access time from RAS# (REG[22h] bit 4 = 0 and bits [3:2] = 00 or 10) t12 Access time from RAS# (REG[22h] bit 4 = 1 and bits [3:2] = 00 or 10) Access time from RAS# (REG[22h] bits [3:2] = 01) t13 t14 t15 t16 Access time from CAS# Access time from CAS# precharge, column address Read Data hold after CAS# low Read Data turn-off delay from RAS# 2 2 Parameter Min 25 5 t1 4 t1 3 t1 2.45 t1 2 t1 1.45 t1 0.45 t1 - 1 t1 - 1 0.45 t1 - 1 0.45 t1 - 1 0.45 t1 0.45 t1 - 1 1 t1 2 t1 - 1 1.45 t1 - 1 1 t1 - 1 2 t1 - 2 1 t1 - 2 1.45 t1 - 2 2 t1 1 t1 1.55 t1 3 t1 - 11 2 t1 - 11 2.45 t1 - 12 t1 - 10 1.45 t1 - 6 0.55 t1 + 1 0.55 t1 Typ Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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7.3.2 EDO-DRAM Write Timing
t1
Memory Clock
t2
t3 R
t4
t5
t6
t8
t9
MA RAS# CAS# WE#
C1
C2
C3 t7
C4
t12 t10 t11 t14 t15
t13
MD(Write)
d1
d2
d3
d4
Figure 7-8: EDO-DRAM Write Timing
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Table 7-8: EDO DRAM Write Timing Symbol t1 Memory clock period Random read or write cycle time (REG[22h] bits [6:5] = 00) t2 Random read or write cycle time (REG[22h] bits [6:5] = 01) Random read or write cycle time (REG[22h] bits [6:5] = 10) Row address setup time (REG[22h] bits [3:2] = 00) t3 Row address setup time (REG[22h] bits [3:2] = 01) Row address setup time (REG[22h] bits [3:2] = 10) t4 t5 t6 t7 t8 t9 Row address hold time (REG[22h] bits [3:2] = 00 or 10) Row address hold time (REG[22h] bits [3:2] = 01) Column address setup time Column address hold time CAS# pulse width CAS# precharge time RAS# hold time RAS# precharge time (REG[22h] bits [3:2] = 00) t10 RAS# precharge time (REG[22h] bits [3:2] = 01) RAS# precharge time (REG[22h] bits [3:2] = 10) RAS# to CAS# delay time (REG[22h] bit 4 = 0 and bits [3:2] = 00 or 10) t11 RAS# to CAS# delay time (REG[22h] bit 4 = 1 and bits [3:2] = 00 or 10) RAS# to CAS# delay time (REG[22h] bits [3:2] = 01) t12 t13 t14 t15 Write command setup time Write command hold time Write Data setup time Write Data hold time Parameter Min 25 5 t1 4 t1 3 t1 2.45 t1 2 t1 1.45 t1 0.45 t1 - 1 t1 - 1 0.45 t1 - 1 0.45 t1 - 1 0.45 t1 0.45 t1 - 1 1 t1 2 t1 - 1 1.45 t1 - 1 1 t1 - 1 2 t1 - 2 1 t1 - 2 1.45 t1 - 2 0.45 t1 - 1 0.45 t1 0.45 t1 - 3 0.45 t1 - 2 2 t1 1 t1 1.55 t1 0.55 t1 + 1 0.55 t1 Typ Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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7.3.3 EDO-DRAM Read-Write Timing
t1
Memory Clock
t2
t3
t4 C1
t5 C2
t6 C3
MA RAS# CAS# WE#
R
t7
t8 t9
t10
MD(Read) MD(Write)
d1
d2 d3
Figure 7-9: EDO-DRAM Read-Write Timing
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Table 7-9: EDO DRAM Read-Write Timing Symbol t1 Memory clock period Random read or write cycle time (REG[22h] bits [6:5] = 00) t2 Random read or write cycle time (REG[22h] bits [6:5] = 01) Random read or write cycle time (REG[22h] bits [6:5] = 10) Row address setup time (REG[22h] bits [3:2] = 00) t3 Row address setup time (REG[22h] bits [3:2] = 01) Row address setup time (REG[22h] bits [3:2] = 10) t4 t5 t6 Row address hold time (REG[22h] bits [3:2] = 00 or 10) Row address hold time (REG[22h] bits [3:2] = 01) Column address setup time Column address hold time RAS# precharge time (REG[22h] bits [3:2] = 00) t7 RAS# precharge time (REG[22h] bits [3:2] = 01) RAS# precharge time (REG[22h] bits [3:2] = 10) RAS# to CAS# delay time (REG[22h] bit 4 = 0 and bits [3:2] = 00 or 10) t8 RAS# to CAS# delay time (REG[22h] bit 4 = 1 and bits [3:2] = 00 or 10) RAS# to CAS# delay time (REG[22h] bits [3:2] = 01) t9 t10 Read Data turn-off delay from WE# Write Data delay from WE# (REG[22h] bit 7 = 0) Write Data delay from WE# (REG[22h] bit 7 = 1) Parameter Min 25 5 t1 4 t1 3 t1 2.45 t1 2 t1 1.45 t1 0.45 t1 - 1 t1 - 1 0.45 t1 - 1 0.45 t1 - 1 2 t1 - 1 1.45 t1 - 1 1 t1 - 1 2 t1 - 2 1 t1 - 2 1.45 t1 - 2 0 1.45 t1 0.45 t1 2 t1 1 t1 1.55 t1 Typ Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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7.3.4 EDO-DRAM CAS Before RAS Refresh Timing
t1
Memory Clock
t2 t3
RAS# CAS#
t4 t6 t5
Figure 7-10: EDO-DRAM CAS Before RAS Refresh Timing
Table 7-10: EDO-DRAM CAS Before RAS Refresh Timing Symbol t1 t2 Memory clock period RAS# to CAS# precharge time (REG[22h] bits [3:2] = 00) RAS# to CAS# precharge time (REG[22h] bits [3:2] = 01 or 10) Random read or write cycle time (REG[22h] bits [6:5] = 00) t3 Random read or write cycle time (REG[22h] bits [6:5] = 01) Random read or write cycle time (REG[22h] bits [6:5] = 10) t4 CAS# precharge time (REG[22h] bits [3:2] = 00) CAS# precharge time (REG[22h] bits [3:2] = 01 or 10) CAS# setup time (REG[22h] bits [3:2] = 00 or 10) CAS# setup time (REG[22h] bits [3:2] = 01) RAS# precharge time (REG[22h] bits [3:2] = 00) t6 RAS# precharge time (REG[22h] bits [3:2] = 01) RAS# precharge time (REG[22h] bits [3:2] = 10) Parameter Min 25 1.45 t1 0.45 t1 5 t1 4 t1 3 t1 2 t1 1 t1 0.45 t1 - 2 1 t1 - 2 2 t1 - 1 1.45 t1 - 1 1 t1 - 1 Typ Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns
t5
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7.3.5 EDO-DRAM Self-Refresh Timing
Stopped for suspend mode Restarted for active mode
t1
Memory Clock
t2
t5
RAS# CAS#
t3 t4
Figure 7-11: EDO-DRAM Self-Refresh Timing
Table 7-11: EDO-DRAM Self-Refresh Timing Symbol t1 t2 t3 Memory clock period RAS# to CAS# precharge time (REG[22h] bits [3:2] = 00) RAS# to CAS# precharge time (REG[22h] bits [3:2] = 01 or 10) CAS# precharge time (REG[22h] bits [3:2] = 00) CAS# precharge time (REG[22h] bits [3:2] = 01 or 10) CAS# setup time (REG[22h] bits [3:2] = 00 or 10) CAS# setup time (REG[22h] bits [3:2] = 01) RAS# precharge time (REG[22h] bits [3:2] = 00) t5 RAS# precharge time (REG[22h] bits [3:2] = 01) RAS# precharge time (REG[22h] bits [3:2] = 10) Parameter Min 25 1.45 t1 0.45 t1 2 t1 1 t1 0.45 t1 - 2 1 t1 - 2 2 t1 - 1 1.45 t1 - 1 1 t1 - 1 Typ Max Units ns ns ns ns ns ns ns ns ns ns
t4
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7.3.6 FPM-DRAM Read Timing
t1
Memory Clock
t2 t3 R t4 C1 t5 C2 t6 C3 t7 t8 t9 C4
MA RAS# CAS#
t10
t11 t12 t13 t14 t15
MD(Read)
d1
d2
d3
d4
Figure 7-12: FPM-DRAM Read Timing
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Table 7-12: FPM DRAM Read Timing Symbol t1 Memory clock Random read or write cycle time (REG[22h] bits [6:5] = 00) t2 Random read or write cycle time (REG[22h] bits [6:5] = 01) Random read or write cycle time (REG[22h] bits [6:5] = 10) Row address setup time (REG[22h] bits [3:2] = 00) t3 Row address setup time (REG[22h] bits [3:2] = 01) Row address setup time (REG[22h] bits [3:2] = 10) t4 t5 t6 t7 t8 t9 Row address hold time (REG[22h] bits [3:2] = 00 or 10) Row address hold time (REG[22h] bits [3:2] = 01) Column address set-up time Column address hold time CAS# pulse width CAS# precharge time RAS# hold time RAS# precharge time (REG[22h] bits [3:2] = 00) t10 RAS# precharge time (REG[22h] bits [3:2] = 01) RAS# precharge time (REG[22h] bits [3:2] = 10) RAS# to CAS# delay time (REG[22h] bit 4 = 1 and bits [3:2] = 00 or 10) t11 RAS# to CAS# delay time (REG[22h] bit 4 = 0 and bits [3:2] = 00 or 10) RAS# to CAS# delay time (REG[22h] bit 4 = 1 and bits [3:2] = 01) RAS# to CAS# delay time (REG[22h] bit 4 = 0 and bits [3:2] = 01) Access time from RAS# (REG[22h] bit 4 = 1 and bits [3:2] = 00 or 10) t12 Access time from RAS# (REG[22h] bit 4 = 0 and bits [3:2] = 00 or 10) Access time from RAS# (REG[22h] bit 4 = 1 and bits [3:2] = 01) Access time from RAS# (REG[22h] bit 4 = 0 and bits [3:2] = 01) t13 t14 t15 Access time from CAS# Access time from CAS# precharge Read Data hold from CAS# or RAS# 2 Parameter Min 40 5 t1 4 t1 3 t1 2 t1 1.45 t1 1 t1 t1 - 1 0.45 t1 - 1 0.45 t1 - 1 0.45 t1 - 1 0.45 t1 0.45 t1 - 1 0.45 t1 2 t1 - 1 1.45 t1 - 1 1 t1 - 1 1.45 t1 - 2 2.45 t1 - 2 1 t1 - 2 2 t1 - 2 1.55 t1 2.55 t1 1 t1 2 t1 2 t1 - 2 3 t1 - 2 1.45 t1 - 2 2.45 t1 - 2 0.45 t1 - 1 1 t1 - 2 0.55 t1 + 1 0.55 t1 Typ Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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7.3.7 FPM-DRAM Write Timing
t1
Memory Clock
t2 t3 t4 R C1 t5 C2 t6 C3 t7 t8 C4 t9
MA RAS# CAS# WE#
t12 t10 t11 t14 t15
t13
MD(Write)
d1
d2
d3
d4
Figure 7-13: FPM-DRAM Write Timing
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Table 7-13: FPM-DRAM Write Timing Symbol t1 Memory clock Random read or write cycle time (REG[22h] bits [6:5] = 00) t2 Random read or write cycle time (REG[22h] bits [6:5] = 01) Random read or write cycle time (REG[22h] bits [6:5] = 10) Row address setup time (REG[22h] bits [3:2] = 00) t3 Row address setup time (REG[22h] bits [3:2] = 01) Row address setup time (REG[22h] bits [3:2] = 10) t4 t5 t6 t7 t8 t9 Row address hold time (REG[22h] bits [3:2] = 00 or 10) Row address hold time (REG[22h] bits [3:2] = 01) Column address set-up time Column address hold time CAS# pulse width CAS# precharge time RAS# hold time RAS# precharge time (REG[22h] bits [3:2] = 00) t10 RAS# precharge time (REG[22h] bits [3:2] = 01) RAS# precharge time (REG[22h] bits [3:2] = 10) RAS# to CAS# delay time (REG[22h] bit 4 = 1 and bits [3:2] = 00 or 10) t11 RAS# to CAS# delay time (REG[22h] bit 4 = 0 and bits [3:2] = 00 or 10) RAS# to CAS# delay time (REG[22h] bit 4 = 1 and bits [3:2] = 01) RAS# to CAS# delay time (REG[22h] bit 4 = 0 and bits [3:2] = 01) t12 t13 t14 t15 Write command setup time Write command hold time Write Data setup time Write Data hold time Parameter Min 40 5 t1 4 t1 3 t1 2 t1 1.45 t1 1 t1 t1 - 1 0.45 t1 - 1 0.45 t1 - 1 0.45 t1 - 1 0.45 t1 0.45 t1 - 1 0.45 t1 2 t1 - 1 1.45 t1 - 1 1 t1 - 1 1.45 t1 - 2 2.45 t1 - 2 1 t1 - 2 2 t1 - 2 0.45 t1 - 1 0.45 t1 0.45 t1 - 3 0.45 t1 - 2 1.55 t1 2.55 t1 1 t1 2 t1 0.55 t1 + 1 0.55 t1 Typ Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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7.3.8 FPM-DRAM Read-Write Timing
t1
Memory Clock
t2 t3 t4 R C1 t5 C2 t6 C3
MA RAS# CAS# WE#
t7
t8 t9
t10
MD(Read) MD(Write)
d1
d2 d3
Figure 7-14: FPM-DRAM Read-Write Timing
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Table 7-14: FPM-DRAM Read-Write Timing Symbol t1 Memory clock Random read or write cycle time (REG[22h] bits [6:5] = 00) t2 Random read or write cycle time (REG[22h] bits [6:5] = 01) Random read or write cycle time (REG[22h] bits [6:5] = 10) Row address setup time (REG[22h] bits [3:2] = 00) t3 Row address setup time (REG[22h] bits [3:2] = 01) Row address setup time (REG[22h] bits [3:2] = 10) t4 t5 t6 Row address hold time (REG[22h] bits [3:2] = 00 or 10) Row address hold time (REG[22h] bits [3:2] = 01) Column address set-up time Column address hold time RAS# precharge time (REG[22h] bits [3:2] = 0) t7 RAS# precharge time (REG[22h] bits [3:2] = 01) RAS# precharge time (REG[22h] bits [3:2] = 10) RAS# to CAS# delay time (REG[22h] bit 4 = 1 and bits [3:2] = 00 or 10) t8 RAS# to CAS# delay time (REG[22h] bit 4 = 0 and bits [3:2] = 00 or 10) RAS# to CAS# delay time (REG[22h] bit 4 = 1 and bits [3:2] = 01) RAS# to CAS# delay time (REG[22h] bit 4 = 0 and bits [3:2] = 01) t9 t10 Read Data turn-off delay from CAS# Write Data enable delay from WE# Parameter Min 40 5 t1 4 t1 3 t1 2 t1 1.45 t1 1 t1 t1 - 1 0.45 t1 - 1 0.45 t1 - 1 0.45 t1 - 1 2 t1 - 1 1.45 t1 - 1 1 t1 - 1 1.45 t1 - 2 2.45 t1 - 2 1 t1 - 2 2 t1 - 2 2 0.45 t1 1.55 t1 2.55 t1 1 t1 2 t1 Typ Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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7.3.9 FPM-DRAM CAS# Before RAS# Refresh Timing
t1
Memory Clock
t2 t3
RAS#
CAS#
t4 t6 t5
Figure 7-15: FPM-DRAM CAS# Before RAS# Refresh Timing
Table 7-15: FPM-DRAM CAS# Before RAS# Refresh Timing Symbol t1 t2 Memory clock RAS# to CAS# precharge time (REG[22h] bits [3:2] = 00) RAS# to CAS# precharge time (REG[22h] bits [3:2] = 01 or 10) Random read or write cycle time (REG[22h] bits [6:5] = 00) t3 Random read or write cycle time (REG[22h] bits [6:5] = 01) Random read or write cycle time (REG[22h] bits [6:5] = 10) t4 t5 t6 CAS# precharge time (REG[22h] bits [3:2] = 00) CAS# precharge time (REG[22h] bits [3:2] = 01 or 10) CAS# setup time (CAS# before RAS# refresh) RAS# precharge time (REG[22h] bits [3:2] = 00) RAS# precharge time (REG[22h] bits [3:2] = 01 or 10) Parameter Min 40 2 t1 1 t1 5 t1 4 t1 3 t1 2 t1 1 t1 0.45 t1 - 2 2.45 t1 - 1 1.45 t1 - 1 Typ Max Units ns ns ns ns ns ns ns ns ns ns ns
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7.3.10 FPM-DRAM Self-Refresh Timing
Stopped for suspend mode Restarted for active mode
t1
Memory Clock
t5 t2
RAS# CAS#
t3 t4
Figure 7-16: FPM-DRAM CBR Self-Refresh Timing
Table 7-16: FPM-DRAM CBR Self-Refresh Timing Symbol t1 t2 t3 t4 t5 Memory clock RAS# to CAS# precharge time (REG[22h] bits [3:2] = 00) RAS# to CAS# precharge time (REG[22h] bits [3:2] = 01 or 10) CAS# precharge time (REG[22h] bits [3:2] = 00) CAS# precharge time (REG[22h] bits [3:2] = 01 or 10) CAS# setup time (CAS# before RAS# refresh) RAS# precharge time (REG[22h] bits [3:2] = 00) RAS# precharge time (REG[22h] bits [3:2] = 01 or 10) Parameter Min 40 2 t1 1 t1 2 t1 1 t1 0.45 t1 - 2 2.45 t1 - 1 1.45 t1 - 1 Typ Max Units ns ns ns ns ns ns ns ns
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7.4 Display Interface 7.4.1 Power-On/Reset Timing
TRESET#
RESET#
LCD ENABLE (REG[0Dh] bit 0)
LCDPWR
Inactive
Active
FPFRAME
Active
FPLINE FPSHIFT FPDAT[15:0] DRDY t1 t2
Active
Figure 7-17: LCD Panel Power-On/Reset Timing
Table 7-17: LCD Panel Power-On/Reset Timing Symbol TRESET# t1 t2 RESET# pulse time LCD Enable bit high to FPLINE, FPSHIFT, FPDAT[15:0], DRDY active FPLINE, FPSHIFT, FPDAT[15:0], DRDY active to LCDPWR, on and FPFRAME active 128 Parameter Min 100 Typ Max Units us ns Frames
TFPFRAME + 6TPCLK
Note Where TFPFRAME is the period of FPFRAME and TPCLK is the period of the pixel clock.
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7.4.2 Suspend Timing
SUSPEND# Software Suspend Note 1
t1
CLKI t2 LCDPWR FPFRAME Active t4 FPLINE DRDY
Note 2 t3 Inactive t5 Active
Active
Inactive
Active
FPSHIFT FPDAT[15:0]
Active t6
Active t7 Allowed
Memory Access
Allowed
Not Allowed
Figure 7-18: LCD Panel Suspend Timing
Table 7-18: LCD Panel Suspend Timing Symbol t1 t2 t3 t4 t5 t6 t7 Parameter LCDPWR inactive to CLKI inactive SUSPEND# active to FPFRAME, LCDPWR inactive First CLKI after SUSPEND# inactive to FPFRAME, LCDPWR active LCDPWR inactive to FPLINE, FPSHIFT, FPDAT[15:0], DRDY active First CLKI after SUSPEND# inactive to FPLINE, FPSHIFT, FPDAT[15:0], DRDY active LCDPWR inactive to Memory Access not allowed First CLKI after SUSPEND# inactive to Memory Access allowed 0 0 8 Min 128 0 Typ Max 1 1 128 Units Frames Frames Frames Frames Frames MCLK MCLK
Note 1. t3, t5, and t7 are measured from the first CLKI after SUSPEND# inactive. 2. CLKI may be active throughout SUSPEND# active. 3. Where MCLK is the period of the memory clock.
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7.4.3 Single Monochrome 4-Bit Panel Timing
VDP FPFRAME FPLINE MOD UD[3:0], UD[3:0]
LINE1 LINE2 LINE3 LINE4 LINE239 LINE240
VNDP
LINE1
LINE2
FPLINE MOD HDP FPSHIFT UD3 UD2 UD1 UD0
1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-317 1-318 1-319 1-320
HNDP
* Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320x240 panel
Figure 7-19: Single Monochrome 4-Bit Panel Timing VDP = VNDP = HDP = HNDP = Vertical Display Period Vertical Non-Display Period Horizontal Display Period Horizontal Non-Display Period = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 = (REG[0Ah] bits [5:0]) + 1 = ((REG[04h] bits [6:0]) + 1)*8Ts = ((REG[05h] bits [4:0]) + 1)*8Ts
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Sync Timing
FPFRAME
t1
t2
t3
t4
FPLINE
t5
MOD
Data Timing
FPLINE
t6 t7 t9 t10 t11 t8 t12
FPSHIFT
t13 1 t14 2
UD[3:0]
Figure 7-20: Single Monochrome 4-Bit Panel A.C. Timing
Table 7-19: Single Monochrome 4-Bit Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 1. 2. 3. 4. 5. 6. Ts t1min t4min t5min t6min t9min Parameter FPFRAME setup to FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE pulse width FPLINE period MOD transition to FPLINE falling edge FPSHIFT falling edge to FPLINE rising edge FPLINE falling edge to FPSHIFT falling edge FPSHIFT period FPSHIFT falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT rising edge FPSHIFT pulse width high FPSHIFT pulse width low UD[3:0] setup to FPSHIFT falling edge UD[3:0] hold to FPSHIFT falling edge Min note 2 9 9 note 3 33 note 5 t14 + 2 4 note 6 18 2 2 2 2 Ts Ts Ts Ts Ts Ts Ts note 4 Ts Typ Max Units Ts (note 1) Ts
= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) = t4min - 9Ts = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] + 33 Ts = [((REG[04h] bits [6:0]) + 1)*8 - 1] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 25] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 16] Ts
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7.4.4 Single Monochrome 8-Bit Panel Timing
VDP
VNDP
FPFRAME FPLINE MOD UD[3:0], LD[3:0]
LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2
FPLINE MOD
HDP HNDP
FPSHIFT UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0
1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-9 1-10 1-11 1-12 1-13 1-14 1-15 1-16 1-633 1-634 1-635 1-636 1-637 1-638 1-639 1-640
* Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel
Figure 7-21: Single Monochrome 8-Bit Panel Timing VDP VNDP HDP HNDP = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 = (REG[0Ah] bits [5:0]) + 1 = ((REG[04h] bits [6:0]) + 1)*8Ts = ((REG[05h] bits [4:0]) + 1)*8Ts
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t1
t2
Sync Timing
FPFRAME
t3 t4
FPLINE
t5
MOD
Data Timing
FPLINE
t6 t7 t9 t10 t11 t8 t12
FPSHIFT
t13 t14 1 2
UD[3:0] LD[3:0]
Figure 7-22: Single Monochrome 8-Bit Panel A.C. Timing
Table 7-20: Single Monochrome 8-Bit Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 1. 2. 3. 4. 5. 6. Ts t1min t4min t5min t6min t9min Parameter FPFRAME setup to FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE pulse width FPLINE period MOD transition to FPLINE falling edge FPSHIFT falling edge to FPLINE rising edge FPLINE falling edge to FPSHIFT falling edge FPSHIFT period FPSHIFT falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT rising edge FPSHIFT pulse width high FPSHIFT pulse width low UD[3:0], LD[3:0] setup to FPSHIFT falling edge UD[3:0], LD[3:0] hold to FPSHIFT falling edge Min note 2 9 9 note 3 33 note 5 t14 + 4 8 note 6 18 4 4 4 4 Typ Max Units Ts (note 1) Ts note 4 Ts Ts Ts Ts Ts Ts Ts Ts
= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) = t4min - 9Ts = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] + 33 Ts = [((REG[04h] bits [6:0]) + 1)*8 - 1] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 23] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 14] Ts
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7.4.5 Single Color 4-Bit Panel Timing
VDP
VNDP
FPFRAME FPLINE MOD UD[3:0]
LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2
FPLINE MOD
HDP
HNDP
FPSHIFT UD3 UD2 UD1 UD0
1-R1 1-G1 1-B1 1-R2 1-G2 1-B2 1-R3 1-G3 1-B3 1-R4 1-G4 1-B4 1-B319 1-R320 1-G320 1-B320
* Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel
Figure 7-23: Single Color 4-Bit Panel Timing VDP VNDP HDP HNDP = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 = (REG[0Ah] bits [5:0]) + 1 = ((REG[04h] bits [6:0]) + 1)*8Ts = ((REG[05h] bits [4:0]) + 1)*8Ts
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t1
Sync Timing
FPFRAME
t3
t2
t4
FPLINE
t5
MOD
Data Timing
FPLINE
t6 t7 t9 t10 t11 t8 t12
FPSHIFT
t13 1 t14 2
UD[3:0]
Figure 7-24: Single Color 4-Bit Panel A.C. Timing
Table 7-21: Single Color 4-Bit Panel A.C. Timing Symbol Parameter t1 FPFRAME setup to FPLINE falling edge t2 FPFRAME hold from FPLINE falling edge t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 1. 2. 3. 4. 5. 6. Ts t1min t4min t5min t6min t9min FPLINE pulse width FPLINE period MOD transition to FPLINE falling edge FPSHIFT falling edge to FPLINE rising edge FPLINE falling edge to FPSHIFT falling edge FPSHIFT period FPSHIFT falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT rising edge FPSHIFT pulse width high FPSHIFT pulse width low UD[3:0], setup to FPSHIFT falling edge UD[3:0], hold from FPSHIFT falling edge Min note 2 9 9 note 3 33 note 5 t14 + 0.5 1 note 6 19 0.45 0.45 0.45 0.45 Ts Ts Ts Ts Ts Ts Ts note 4 Ts Typ Max Units Ts (note 1) Ts
= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) = t4min - 9Ts = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] + 33 Ts = [((REG[04h] bits [6:0])+1)*8 - 1] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 26] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 17] Ts
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7.4.6 Single Color 8-Bit Panel Timing (Format 1)
VDP
VNDP
FPFRAME FPLINE
UD[3:0], LD[3:0]
LINE1
LINE2
LINE3
LINE4
LINE479 LINE480
LINE1
LINE2
FPLINE
HDP HNDP
FPSHIFT
FPSHIFT2 UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0
1-R1 1-B1 1-G2 1-R3 1-B3 1-G4 1-R5 1-B5 1-G1 1-R2 1-B2 1-G3 1-R4 1-B4 1-G5 1-R6 1-G6 1-R7 1-B7 1-G8 1-R9 1-B9 1-G10 1-R11 1-B6 1-G7 1-R8 1-B8 1-G9 1-R10 1-B10 1-B11 1-G12 1-R13 1-B13 1-G14 1-R15 1-B15 1-R12 1-B12 1-G13 1-R14 1-B14 1-G15 1-R16 1-B16 1-R636 1-B636 1-G637 1-R638 1-B638 1-G639 1-R640 1-B640
1-G11 1-G16
* Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel
Figure 7-25: Single Color 8-Bit Panel Timing (Format 1) VDP VNDP HDP HNDP = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 = (REG[0Ah] bits [5:0]) + 1 = ((REG[04h] bits [6:0]) + 1)*8Ts = ((REG[05h] bits [4:0]) + 1)*8Ts
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t1
Sync Timing
FPFRAME
t3
t2
t4
FPLINE
Data Timing
FPLINE
t5a t5b t8a t9 t6 t10 t7 t11
FPSHIFT
t8b
FPSHIFT2
t12 t13 1 2
UD[3:0] LD[3:0]
Figure 7-26: Single Color 8-Bit Panel A.C. Timing (Format 1)
Table 7-22: Single Color 8-Bit Panel A.C. Timing (Format 1) Symbol t1 t2 t3 t4 t5a t5b t6 t7 t8a t8b t9 t10 t11 t12 t13 1. 2. 3. 4. 5. 6. 7. Ts t1min t4min t5min t5min t8min t8min Parameter FPFRAME setup to FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE pulse width FPLINE period FPSHIFT2 falling edge to FPLINE rising edge FPSHIFT falling edge to FPLINE rising edge FPLINE falling edge to FPSHIFT2 rising, FPSHIFT falling edge FPSHIFT2, FPSHIFT period FPSHIFT falling edge to FPLINE falling edge FPSHIFT2 falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT rising edge FPSHIFT2, FPSHIFT pulse width high FPSHIFT2, FPSHIFT pulse width low UD[3:0], LD[3:0] setup to FPSHIFT2 rising, FPSHIFT falling edge UD[3:0], LD[3:0] hold from FPSHIFT2 rising, FPSHIFT falling edge Min note 2 9 9 note 3 note 4 note 5 t14 + 2 4 note 6 note 7 18 2 2 1 1 Ts Ts Ts Ts Ts Ts Ts Typ Max Units Ts (note 1) Ts
= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) = t4min - 9Ts = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 27]+T11 Ts = [((REG[05h] bits [4:0]) + 1)*8 - 27] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 18] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 18]+T11 Ts
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7.4.7 Single Color 8-Bit Panel Timing (Format 2)
VDP
VNDP
FPFRAME FPLINE MOD UD[3:0], LD[3:0]
LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2
FPLINE MOD
HDP
HNDP
FPSHIFT UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0
1-R1 1-G1 1-B1 1-R2 1-G2 1-B2 1-R3 1-G3 1-B3 1-R4 1-G4 1-B4 1-R5 1-G5 1-B5 1-R6 1-G6 1-B6 1-R7 1-G7 1-B7 1-R8 1-G8 1-B8 1-G638 1-B638 1-R639 1-G639 1-B639 1-R640 1-G640 1-B640
* Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel
Figure 7-27: Single Color 8-Bit Panel Timing (Format 2) VDP VNDP HDP HNDP = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 = (REG[0Ah] bits [5:0]) + 1 = ((REG[04h] bits [6:0]) + 1)*8Ts = ((REG[05h] bits [4:0]) + 1)*8Ts
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Sync Timing
FPFRAME
t1
t2
t4
t3
FPLINE
t5
MOD
Data Timing
FPLINE
t6 t8 t7 t14 t11 t9 t10
FPSHIFT
t12 t13 1 2
UD[3:0] LD[3:0]
Figure 7-28: Single Color 8-Bit Panel A.C. Timing (Format 2)
Table 7-23: Single Color 8-Bit Panel A.C. Timing (Format 2) Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 1. 2. 3. 4. 5. 6. Ts t1min t3min t5min t6min t7min Parameter FPFRAME setup to FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE period FPLINE pulse width MOD transition to FPLINE falling edge FPSHIFT falling edge to FPLINE rising edge FPSHIFT falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT falling edge FPSHIFT period FPSHIFT pulse width low FPSHIFT pulse width high UD[3:0], LD[3:0] setup to FPSHIFT falling edge UD[3:0], LD[3:0] hold to FPSHIFT falling edge FPLINE falling edge to FPSHIFT rising edge Min note 2 9 note 3 9 33 note 5 note 6 t14 + 2 2 1 1 1 1 18 Ts Ts Ts Ts Ts Ts note 4 Ts Ts Typ Max Units Ts (note 1)
= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) = t3min - 9Ts = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] + 33 Ts = [((REG[04h] bits [6:0])+1)*8 - 1] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 26] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 17] Ts
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7.4.8 Single Color 16-Bit Panel Timing
VDP
VNDP
FPFRAME FPLINE MOD UD[7:0], LD[7:0]
LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2
FPLINE MOD
HDP HNDP
FPSHIFT UD7 UD6 UD5 UD4 UD3 UD2 UD1 UD0 LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0
1-R1 1-B1 1-G2 1-R3 1-B3 1-G4 1-R5 1-B5 1-G1 1-R2 1-B2 1-G3 1-R4 1-B4 1-G5 1-R6 1-G6 1-R7 1-B7 1-G8 1-R9 1-B9 1-B11 1-G12 1-R13 1-B13 1-G14 1-R15 1-G635 1-G636 1-R637 1-B637 1-G638 1-R639 1-B639 1-G640 1-R636 1-B636 1-G637 1-R638 1-B638 1-G639 1-R640 1-B640
1-G10 1-B15 1-R11 1-B6 1-G7 1-R8 1-B8 1-G9 1-R10 1-G16 1-R12 1-B12 1-G13 1-R14 1-B14 1-G15
1-B10 1-R16 1-G11 1-B16
* Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel
Figure 7-29: Single Color 16-Bit Panel Timing VDP VNDP HDP HNDP = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 = (REG[0Ah] bits [5:0]) + 1 = ((REG[04h] bits [6:0]) + 1)*8Ts = ((REG[05h] bits [4:0]) + 1)*8Ts
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Sync Timing
FPFRAME
t1
t2
t4
t3
FPLINE
t5
MOD
Data Timing
FPLINE
t6 t8 t7 t14 t11 t9 t10
FPSHIFT
t12 t13 1 2
UD[7:0] LD[7:0]
Figure 7-30: Single Color 16-Bit Panel A.C. Timing
Table 7-24: Single Color 16-Bit Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 1. 2. 3. 4. 5. 6. Ts t1min t3min t5min t6min t7min Parameter FPFRAME setup to FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE period FPLINE pulse width MOD transition to FPLINE falling edge FPSHIFT falling edge to FPLINE rising edge FPSHIFT falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT falling edge FPSHIFT period FPSHIFT pulse width low FPSHIFT pulse width high UD[7:0], LD[7:0] setup to FPSHIFT falling edge UD[7:0], LD[7:0] hold to FPSHIFT falling edge FPLINE falling edge to FPSHIFT rising edge Min note 2 9 note 3 9 33 note 5 note 6 t14 + 3 5 2 2 2 2 18 Ts Ts Ts Ts Ts Ts Ts note 4 Ts Ts Typ Max Units Ts (note 1)
= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) = t3min - 9Ts = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] + 33 Ts = [((REG[04h] bits [6:0])+1)*8 - 1] Ts = [(REG[05h] bits [4:0]) + 1)*8 - 25] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 16] Ts
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7.4.9 Dual Monochrome 8-Bit Panel Timing
VDP
VNDP
FPFRAME FPLINE MOD UD[3:0], LD[3:0]
LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 LINE 1/241 LINE 2/242
FPLINE MOD
HDP HNDP
FPSHIFT UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0
1-1 1-2 1-3 1-4 241-1 241-2 241-3 241-4 1-5 1-6 1-7 1-8 241-5 241-6 241-7 241-8 1-637 1-638 1-639 1-640 241-637 241-638 241-639 241-640
* Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel
Figure 7-31: Dual Monochrome 8-Bit Panel Timing VDP VNDP HDP HNDP = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 = (REG[0Ah] bits [5:0]) + 1 = ((REG[04h] bits [6:0]) + 1)*8Ts = ((REG[05h] bits [4:0]) + 1)*8Ts
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Sync Timing
FPFRAME
t1
t2
t4
t3
FPLINE
t5
MOD
Data Timing
FPLINE
t6 t8 t7 t14 t11 t9 t10
FPSHIFT
t12 t13 1 2
UD[3:0] LD[3:0]
Figure 7-32: Dual Monochrome 8-Bit Panel A.C. Timing
Table 7-25: Dual Monochrome 8-Bit Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 1. 2. 3. 4. 5. 6. Ts t1min t3min t5min t6min t7min Parameter FPFRAME setup to FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE period FPLINE pulse width MOD transition to FPLINE falling edge FPSHIFT falling edge to FPLINE rising edge FPSHIFT falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT falling edge FPSHIFT period FPSHIFT pulse width low FPSHIFT pulse width high UD[3:0], LD[3:0] setup to FPSHIFT falling edge UD[3:0], LD[3:0] hold to FPSHIFT falling edge FPLINE falling edge to FPSHIFT rising edge Min note 2 9 note 3 9 33 note 5 note 6 t14 + 2 4 2 2 2 2 10 Typ Max Units Ts (note 1) Ts Ts
note 4
Ts Ts Ts Ts Ts Ts Ts
= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) = t3min - 9Ts = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] + 33 Ts = [((REG[04h] bits [6:0])+1)*8 - 1] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 17] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 8] Ts
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7.4.10 Dual Color 8-Bit Panel Timing
VDP
VNDP
FPFRAME FPLINE MOD UD[3:0], LD[3:0]
LINE 1/241 LINE 2/242 LINE 239/479 LINE 240/480 LINE 1/241
FPLINE MOD
HDP HNDP
FPSHIFT UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0
1-R1 1-G1 1-B1 1-R2 1-G 2 1-B2 1-R 3 1-G3 1-B 3 1-R4 1-G4 1-B4 1-R 5 1-G5 1-B5 1-R6 1-G6 1-B6 1-R7 1-G7 1-B7 1-R8 1-G8 1-B8 1-B639 1-R640 1-G640 1-B640 2 41B639 241R640 241G640 2 41B640
241-R 1 241-G2 241-B 3
241-R5 241-G6 241-B7
241-G1 24 1-B2 241-R 4 241-G 5 241-B6 241-R8 241-B1 241-R3 241-G4 241-B5 241-R7 241-G8 241-R 2 241-G3 241-B4 241-R 6 241-G7 241-B8
* Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel
Figure 7-33: Dual Color 8-Bit Panel Timing VDP VNDP HDP HNDP = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 = (REG[0Ah] bits [5:0]) + 1 = ((REG[04h] bits [6:0]) + 1)*8Ts = ((REG[05h] bits [4:0]) + 1)*8Ts
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t1
t2
Sync Timing
FPFRAME
t4 t3
FPLINE
t5
MOD
Data Timing
FPLINE
t6 t8 t7 t14 t11 t9 t10
FPSHIFT
t12 t13 1 2
UD[3:0] LD[3:0]
Figure 7-34: Dual Color 8-Bit Panel A.C. Timing
Table 7-26: Dual Color 8-Bit Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 1. 2. 3. 4. 5. 6. Ts t1min t3min t5min t6min t7min Parameter FPFRAME setup to FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE period FPLINE pulse width MOD transition to FPLINE falling edge FPSHIFT falling edge to FPLINE rising edge FPSHIFT falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT falling edge FPSHIFT period FPSHIFT pulse width low FPSHIFT pulse width high UD[3:0], LD[3:0] setup to FPSHIFT falling edge UD[3:0], LD[3:0] hold to FPSHIFT falling edge FPLINE falling edge to FPSHIFT rising edge Min note 2 9 note 3 9 33 note 5 note 6 t14 + 1 1 0.45 0.45 0.45 0.45 11 Ts Ts Ts Ts Ts Ts Ts note 4 Ts Ts Typ Max Units Ts (note 1)
= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) = t3min - 9Ts = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] + 33 Ts = [((REG[04h] bits [6:0])+1)*8 - 1] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 18] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 9] Ts
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7.4.11 Dual Color 16-Bit Panel Timing
VDP
VNDP
FPFRAME FPLINE MOD UD[7:0], LD[7:0]
LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 LINE 1/241 LINE 2/242
FPLINE MOD
HDP HNDP
FPSHIFT UD7, LD7 UD6, LD6 UD5, LD5 UD4, LD4 UD3, LD3 UD2, LD2 UD1, LD1 UD0, LD0
1-R1, 241-R1 1-G1, 241-G1 1-B1, 241-B 1 1-R2, 241-R2 1-G2, 241-G2 1-B2, 241-B 2 1-R3, 241-R3 1-G3, 241-G3 1-B3, 241-B 3 1-R4, 241-R4 1-G4, 241-G 4 1-B4, 241-B 4 1-R5, 241-R5 1-G5, 241-G 5 1-B5, 241-B5 1-R6, 241-R6 1-G638, 241-G638 1-B638, 241-B638 1-R639, 241-R639 1-G639, 241-G63 9 1-B639, 241-B639 1-R640, 241-R640 1-G640, 241-G640 1-B640, 241-B640
* Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel
Figure 7-35: Dual Color 16-Bit Panel Timing VDP VNDP HDP HNDP = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 = (REG[0Ah] bits [5:0]) + 1 = ((REG[04h] bits [6:0]) + 1)*8Ts = ((REG[05h] bits [4:0]) + 1)*8Ts
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t1
t2
Sync Timing
FPFRAME
t4 t3
FPLINE
t5
MOD
Data Timing
FPLINE
t6 t8 t7 t14 t11 t9 t10
FPSHIFT
t12 t13 1 2
UD[7:0] LD[7:0]
Figure 7-36: Dual Color 16-Bit Panel A.C. Timing
Table 7-27: Dual Color 16-Bit Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 1. 2. 3. 4. 5. 6. Ts t1min t3min t5min t6min t7min Parameter FPFRAME setup to FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE period FPLINE pulse width MOD transition to FPLINE falling edge FPSHIFT falling edge to FPLINE rising edge FPSHIFT falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT falling edge FPSHIFT period FPSHIFT pulse width low FPSHIFT pulse width high UD[7:0], LD[7:0] setup to FPSHIFT falling edge UD[7:0], LD[7:0] hold to FPSHIFT falling edge FPLINE falling edge to FPSHIFT rising edge Min note 2 9 note 3 9 33 note 5 note 6 t14 + 2 2 1 1 1 1 10 Ts Ts Ts Ts Ts Ts note 4 Ts Ts Typ Max Units Ts (note 1)
= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) = t3min - 9Ts = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] + 33 Ts = [((REG[04h] bits [6:0])+1)*8 - 1] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 18] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 9] Ts
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7.4.12 16-Bit TFT Panel Timing
VNDP
VDP
FPFRAME FPLINE R[5:1], G[5:0], B[5:1] DRDY
LINE480 LINE1 LINE480
FPLINE
HNDP1 HDP HNDP2
FPSHIFT
DRDY
R[5:1] G [5:0] B[5:1]
1-1 1-1 1-1
1-2 1-2 1-2
1-640 1-640 1-640
Note: DRDY is used to indicate the first pixel Example Timing for 640x480 panel
Figure 7-37: 16-Bit TFT Panel Timing VDP VNDP HDP HNDP = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 = (REG[0Ah] bits [5:0]) + 1 = ((REG[04h] bits [6:0]) + 1)*8Ts = HNDP1 + HNDP2 = ((REG[05h] bits [4:0]) + 1)*8Ts
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t8 t9
FPFRAME
t12
FPLINE
t6
FPLINE
t7 t17 t15
DRDY
t14 t1 t2 t3 t11 t13 t16
FPSHIFT
t4 t5 1 2 t10 639 640
R[5:1] G[5:0] B[5:1]
Note: DRDY is used to indicate the first pixel
Figure 7-38: TFT A.C. Timing
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Table 7-28: TFT A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Ts t6min t7min t8 min t9min t10min t12min t14min t15min t17min FPSHIFT period FPSHIFT pulse width high FPSHIFT pulse width low data setup to FPSHIFT falling edge data hold from FPSHIFT falling edge FPLINE cycle time FPLINE pulse width low FPFRAME cycle time FPFRAME pulse width low horizontal display period FPLINE setup to FPSHIFT falling edge FPFRAME falling edge to FPLINE falling edge phase difference DRDY to FPSHIFT falling edge setup time DRDY pulse width DRDY falling edge to FPLINE falling edge DRDY hold from FPSHIFT falling edge FPLINE Falling edge to DRDY active Parameter Min 1 0.45 0.45 0.45 0.45 note 2 note 3 note 4 note 5 note 6 0.45 note 7 0.45 note 8 note 9 0.45 note 10 250 Ts Ts Ts Ts Typ Max Units Ts (note 1) Ts Ts Ts Ts
= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0])+1)*8] Ts = [((REG[07h] bits [3:0])+1)*8] Ts = [((REG[09h] bits [1:0], REG[08h] bits [7:0])+1) + ((REG[0Ah] bits [5:0])+1)] lines = [((REG[0Ch] bits [2:0])+1)] lines = [((REG[04h] bits [6:0])+1)*8] Ts = [((REG[06h] bits [4:0])+1)*8] Ts = [((REG[04h] bits [6:0])+1)*8] Ts = [((REG[06h] bits [4:0])+1)*8 - 2] Ts = [((REG[05h] bits [4:0])+1)*8 - ((REG[06h] bits [4:0])+1)*8 + 2]
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7.4.13 CRT Timing
Example Timing for 640x480 CRT
VNDP
VDP
VRTC HRTC DACP[7:0] BLANK#
LINE480 LINE1 LINE480
HRTC
HNDP1 HDP HNDP2
DACCLK
BLANK#
DACD[7:0]
1-1
1-2
1-640
Figure 7-39: CRT Timing VDP VNDP HDP HNDP = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 = (REG[0Ah] bits [5:0]) + 1 = ((REG[04h] bits [6:0]) + 1)*8Ts = ((REG[05h] bits [4:0]) + 1)*8Ts = HNDP1 + HNDP2
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t8 t9
VRTC
t12
HRTC
t6
HRTC
t7
t15
BLANK#
t1 t2 t3 t11 t13
t14 t16
DACCLK
t4
t5 1 2 t10 639 640
DACD[7:0]
Figure 7-40: CRT A.C. Timing
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Table 7-29: CRT A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 1. 2. 3. 4. 5. 6. 7. 8. 9. Ts t6min t7min t8 min t9min t10min t12min t14min t15min DACCLK period DACCLK pulse width high DACCLK pulse width low data setup to DACCLK rising edge data hold from DACCLK rising edge HRTC cycle time HRTC pulse width (shown active low) VRTC cycle time VRTC pulse width (shown active low) horizontal display period HRTC setup to DACCLK rising edge VRTC falling edge to FPLINE falling edge phase difference BLANK# to DACCLK rising edge setup time BLANK# pulse width BLANK# falling edge to HRTC falling edge BLANK# hold from DACCLK rising edge Parameter Min 1 0.45 0.45 0.45 0.45 note 2 note 3 note 4 note 5 note 6 0.45 note 7 0.45 note 8 note 9 0.45 Ts Ts Ts Typ Max Units Ts (note 1) Ts Ts Ts Ts
= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0])+1)*8] Ts = [((REG[07h] bits [3:0])+1)*8] Ts = [((REG[09h] bits [1:0], REG[08h] bits [7:0])+1) + ((REG[0Ah] bits [6:0])+1)] lines = [((REG[0Ch] bits [2:0])+1)] lines = [((REG[04h] bits [6:0])+1)*8] Ts = [((REG[06h] bits [4:0])+1)*8] Ts = [((REG[04h] bits [6:0])+1)*8] Ts = [((REG[06h] bits [4:0])+1)*8 - 2] Ts
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7.4.14 External RAMDAC Read / Write Timing
Read
AB[20:0] CS# M/R# DACRS[1:0]
t1
t2
Valid RD# Command (depends on CPU bus)
t3 t4
DACRD#
Write
Valid WR# command (depends on CPU bus)
t5
DACWR#
t6
Figure 7-41: Generic Bus RAMDAC Read / Write Timing Table 7-30: Generic Bus RAMDAC Read / Write Timing Symbol TBCLK t1 t2 t3 t4 t5 t6 Bus clock period AB[20:0], CS#, M/R# delay to DACRS[1:0] DACRS[1:0] hold from AB[20:0], CS#, M/R# negated Valid RD# command to DACRS[1:0] delay DACRD# hold from valid RD# command negated Valid WR# command to DACWR# delay DACWR# pulse width low 8 3 2 TBCLK 2.45 TBCLK 2.55 TBCLK Parameter Min 30 10 10 33 14 Typ Max Units ns ns ns ns ns ns ns
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8 Registers
8.1 Register Mapping
The S1D13504 registers are all memory mapped. The system must provide the external address decoding through the CS# and M/R# input pins. When CS# = 0 and M/R# = 0, the registers are mapped by address bits AB[5:0], e.g. REG[00h] is mapped to AB[5:0] = 000000, REG[01h] is mapped to AB[5:0] = 000001. See the table below:
Table 8-1: S1D13504 Addressing CS# M/R# Register access: 0 0 * REG[00h] is addressed when AB[5:0] = 0 * REG[01h] is addressed when AB[5:0] = 1 * REG[n] is addressed when AB[5:0] = n Memory access: the 2M byte display buffer is addressed by AB[20:0] S1D13504 not selected Access
0 1
1 X
8.2 Register Descriptions
Note Unless specified otherwise, all register bits are reset to 0 during power up. Reserved bits should be written 0 when programming unless otherwise noted.
8.2.1 Revision Code Register
Revision Code Register
REG[00h] Product Code Product Code Product Code Product Code Product Code Product Code Revision Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Code Bit 1 RO Revision Code Bit 0
bits 7-2 bits 1-0
Product Code Bits [5:0] This is a read-only register that indicates the product code of the chip. The product code is 000001. Revision Code Bits [1:0] This is a read-only register that indicates the revision code of the chip. The revision code is 00.
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8.2.2 Memory Configuration Registers
Memory Configuration Register
REG[01h] n/a Refresh Rate Bit 2 Refresh Rate Bit 1 Refresh Rate Bit 0 n/a WE# Control n/a RW Memory Type
bits 6-4
DRAM Refresh Rate Select Bits [2:0] These bits specify the amount of divide from the input clock (CLKI) to generate the DRAM refresh clock rate, which is equal to 2(ValueOfTheseBits + 6).
Table 8-2: DRAM Refresh Rate Selection Refresh Rate Bits [2:0] 000 001 010 011 100 101 110 111 CLKI Divide Amount 64 128 256 512 1024 2048 4096 8192 Refresh Rate for 33MHz CLKI 520 kHz 260 kHz 130 kHz 65 kHz 33 kHz 16 kHz 8 kHz 4 kHz DRAM Refresh Time/256 Cycles 0.5 ms 1 ms 2 ms 4 ms 8 ms 16 ms 32 ms 64 ms
bit 2 bit 0
WE# Control When this bit = 1, 2-WE# DRAM is selected. When this bit = 0 2-CAS# DRAM is selected. Memory Type When this bit = 1, FPM-DRAM is selected. When this bit = 0, EDO-DRAM is selected. This bit should be changed only when there are no read/write DRAM cycles. This condition occurs when both the Display FIFO is disabled (REG[23h] bit 7 = 1) and the Half Frame Buffer is disabled (REG[1Bh] bit 0 = 1). For programming information, see S1D13504 Programming Notes and Examples, document number X19A-G-002-xx.
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8.2.3 Panel/Monitor Configuration Registers
Panel Type Register
REG[02h] n/a n/a Panel Data Width Bit 1 Panel Data Width Bit 0 Panel Data Color/Mono Format Select Panel Select Dual/Single Panel Select RW TFT/Passive LCD Panel Select
bits 5-4
Panel Data Width Bits [1:0] These bits select passive LCD/TFT panel data width size.
Table 8-3: Panel Data Width Selection Panel Data Width Bits [1:0] 00 01 10 11 Passive LCD Panel Data Width Size 4-bit 8-bit 16-bit Reserved TFT Panel Data Width Size 9-bit 12-bit 16-bit Reserved
bit 3
Panel Data Format Select When this bit = 1, 8-bit single color passive LCD panel data format 2 is selected. This bit must be set to 0 for all other LCD panel formats. Color/Mono Panel Select When this bit = 1, color passive LCD panel is selected. When this bit = 0, monochrome passive LCD panel is selected. Dual/Single Panel Select When this bit = 1, dual passive LCD panel is selected. When this bit = 0, single passive LCD panel is selected. Setting this bit for single panel mode should be done only when the Half Frame Buffer is idle. The Half Frame Buffer is idle during vertical non-display periods or while in suspend mode. For programming information, see S1D13504 Programming Notes and Examples, document number X19A-G-002-xx. TFT/Passive LCD Panel Select When this bit = 1, TFT panel is selected. When this bit = 0, passive LCD panel is selected.
bit 2
bit 1
bit 0
MOD Rate Register
REG[03h] n/a n/a RW MOD Rate Bit MOD Rate Bit MOD Rate Bit MOD Rate Bit MOD Rate Bit MOD Rate Bit 5 4 3 2 1 0
bits 5-0
MOD Rate Bits [5:0] For a non-zero value these bits specify the number of FPLINE between toggles of the MOD output signal. When these bits are all 0's the MOD output signal toggles every FPFRAME. These bits are for passive LCD panels only.
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Horizontal Display Width Register
REG[04h] n/a RW Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Display Width Display Width Display Width Display Width Display Width Display Width Display Width Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
bits 6-0
Horizontal Display Width Bits [6:0] These bits specify the LCD panel and/or the CRT horizontal display width as follows. Contents of this Register = (Horizontal Display Width / 8) - 1 For passive LCD panels the Horizontal Display Width must be divisible by 16, and for TFT LCD panels/CRTs the Horizontal Display Width must be divisible by 8. The maximum horizontal display width is 1024 pixels. Note This register must be programmed such that REG[04h] 3 (32 pixels)
Horizontal Non-Display Period Register
REG[05h] n/a n/a n/a Horizontal Non-Display Period Bit 4 Horizontal Non-Display Period Bit 3 Horizontal Non-Display Period Bit 2 Horizontal Non-Display Period Bit 1 RW Horizontal Non-Display Period Bit 0
bits 4-0
Horizontal Non-Display Period Bits [4:0] These bits specify the horizontal non-display period width in 8-pixel resolution as follows. Contents of this Register = (Horizontal Non-Display Period / 8) - 1 The minimum value which should be programmed into this register is 3 (32 pixels). The maximum value which can be programmed into this register is 1F, which gives a horizontal non-display period width of 256 pixels. Note This register must be programmed such that REG[05h] 3 and (REG[05h] + 1) (REG[06h] + 1) + (REG[07h] bits [3:0] + 1)
HRTC/FPLINE Start Position Register
REG[06h] n/a n/a n/a HRTC/ FPLINE Start Position Bit 4 HRTC/ FPLINE Start Position Bit 3 HRTC/ FPLINE Start Position Bit 2 HRTC/ FPLINE Start Position Bit 1 RW HRTC/ FPLINE Start Position Bit 0
bits 4-0
HRTC/FPLINE Start Position Bits [4:0] For CRTs and TFTs, these bits specify the delay from the start of the horizontal non-display period to the leading edge of the HRTC pulse and FPLINE pulse respectively. Contents of this Register = (HRTC/FPLINE Start Position / 8) - 1 The maximum HRTC start delay is 256 pixels. Note This register must be programmed such that (REG[05h] + 1) (REG[06h] + 1) + (REG[07h] bits [3:0] + 1)
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HRTC/FPLINE Pulse Width Register
REG[07h] HRTC Polarity Select FPLINE Polarity Select n/a n/a RW HRTC/ HRTC/ HRTC/ HRTC/ FPLINE Pulse FPLINE Pulse FPLINE Pulse FPLINE Pulse Width Bit 3 Width Bit 2 Width Bit 1 Width Bit 0
bit 7
HRTC Polarity Select For CRTs, this bit selects the polarity of the HRTC. When this bit = 1, the HRTC pulse is active high. When this bit = 0, the HRTC pulse is active low. FPLINE Polarity Select This bit selects the polarity of the FPLINE for TFT and passive LCD. When this bit = 1, the FPLINE pulse is active high for TFT and active low for passive LCD. When this bit = 0, the FPLINE pulse is active low for TFT and active high for passive LCD.
Table 8-4: FPLINE Polarity Selection FPLINE Polarity Select 0 1 Passive LCD FPLINE Polarity active high active low TFT FPLINE Polarity active low active high
bit 6
bits 3-0
HRTC/FPLINE Pulse Width Bits [3:0] For CRTs and TFTs, these bits specify the pulse width of HRTC and FPLINE respectively. For passive LCDs, FPLINE is automatically created and these bits have no effect. HRTC/FPLINE pulse width (pixels) = (HRTC/FPLINE Pulse Width Bits [3:0] + 1) x 8. The maximum HRTC pulse width is 128 pixels. Note This register must be programmed such that (REG[05h] + 1) (REG[06h] + 1) + (REG[07h] bits [3:0] + 1)
Vertical Display Height Register 0
REG[08h] Vertical Display Height Bit 7 Vertical Display Height Bit 6 Vertical Display Height Bit 5 Vertical Display Height Bit 4 Vertical Display Height Bit 3 Vertical Display Height Bit 2 Vertical Display Height Bit 1 RW Vertical Display Height Bit 0
Vertical Display Height Register 1
REG[09h] n/a n/a n/a n/a n/a n/a Vertical Display Height Bit 9 RW Vertical Display Height Bit 8
REG[08h] bits 7-0 REG[09h] bits 1-0
Vertical Display Height Bits [9:0] These bits specify the LCD panel and/or the CRT vertical display height, in 1-line resolution. For a dual LCD panel only configuration, this register should be programmed to half the panel size. Vertical display height in number of lines = (ContentsOfThisRegister) + 1. The maximum vertical display height is 1024 lines.
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Vertical Non-Display Period Register
REG[0Ah] Vertical Non-Display Period Status (RO) Vertical Non-Display Period Bit 5 Vertical Non-Display Period Bit 4 Vertical Non-Display Period Bit 3 Vertical Non-Display Period Bit 2 Vertical Non-Display Period Bit 1 RW Vertical Non-Display Period Bit 0
n/a
bit 7
Vertical Non-Display Period Status This is a read-only status bit. A "1" indicates that a vertical non-display period is occurring. A "0" indicates that display output is in a vertical display period. Note When configured for a dual panel, this bit will toggle at twice the frame rate.
bits 5-0
Vertical Non-Display Period Bits [5:0] These bits specify the vertical non-display period height in 1-line resolution. Vertical non-display period height in number of lines = (ContentsOfThisRegister) + 1. The maximum vertical non-display period height is 64 lines. Note This register must be programmed such that REG[0Ah] 1 and (REG[0Ah] bits [5:0] + 1) (REG[0Bh] + 1) + (REG[0Ch] bits [2:0] + 1)
VRTC/FPFRAME Start Position Register
REG[0Bh] VRTC/ FPFRAME Start Position Bit 5 VRTC/ FPFRAME Start Position Bit 4 VRTC/ FPFRAME Start Position Bit 3 VRTC/ FPFRAME Start Position Bit 2 VRTC/ FPFRAME Start Position Bit 1 RW VRTC/ FPFRAME Start Position Bit 0
n/a
n/a
bits 5-0
VRTC/FPFRAME Start Position Bits [5:0] For CRTs and TFTs, these bits specify the delay in lines from the start of the vertical non-display period to the leading edge of the VRTC pulse and FPFRAME pulse respectively. For passive LCDs, FPFRAME is automatically created and these bits have no effect. VRTC/FPFRAME start position (lines) = VRTC/FPFRAME Start Position Bits [5:0] + 1. The maximum VRTC start delay is 64 lines. Note This register must be programmed such that (REG[0Ah] bits [5:0] + 1) (REG[0Bh] + 1) + (REG[0Ch] bits [2:0] + 1)
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VRTC/FPFRAME Pulse Width Register
REG[0Ch] FPFRAME VRTC Polarity Polarity Select Select VRTC/ FPFRAME Pulse Width Bit 2 VRTC/ FPFRAME Pulse Width Bit 1 RW VRTC/ FPFRAME Pulse Width Bit 0
n/a
n/a
n/a
bit 7
VRTC Polarity Select For CRTs, this bit selects the polarity of the VRTC. When this bit = 1, the VRTC pulse is active high. When this bit = 0, the VRTC pulse is active low. FPFRAME Polarity Select This bit selects the polarity of the FPFRAME for TFT and passive LCD. When this bit = 1, the FPFRAME pulse is active high for TFT and active low for passive LCD. When this bit = 0, the FRAME pulse is active low for TFT and active high for passive LCD.
Table 8-5: FPFRAME Polarity Selection FPFRAME Polarity Select 0 1 Passive LCD FPFRAME Polarity active high active low TFT FPFRAME Polarity active low active high
bit 6
bits 2-0
VRTC/FPFRAME Pulse Width Bits [2:0] For CRTs and TFTs, these bits specify the pulse width of VRTC and FPFRAME respectively. For passive LCDs, FPFRAME is automatically created and these bits have no effect. VRTC/FPFRAME pulse width (lines) = VRTC/FPFRAME Pulse Width Bits [2:0] + 1. The maximum VRTC pulse width is 8 lines. Note This register must be programmed such that (REG[0Ah] bits [5:0] + 1) (REG[0Bh] + 1) + (REG[0Ch] bits [2:0] + 1)
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8.2.4 Display Configuration Registers
Display Mode Register
REG[0Dh] Simultaneous Display Option Select Bit 1 Simultaneous Number Of Display Bits/Pixel Option Select Select Bit 2 Bit 0 Number Of Bits/Pixel Select Bit 1 Number Of Bits/Pixel Select Bit 0 RW
n/a
CRT Enable
LCD Enable
bits 6-5
Simultaneous Display Option Select Bits [1:0] These bits are used to select one of four different simultaneous display mode options: Normal, Line Doubling, Interlace, or Even Scan Only. The purpose of these modes is to manipulate the vertical resolution of the image so that it fits on both CRT, typically 640 x 480, and LCD. The following gives descriptions of the four modes using a 640x480 CRT as an example:
Table 8-6: Simultaneous Display Option Selection Simultaneous Display Option Select Bits [1:0] 00 01 10 11 Simultaneous Display Option Normal Line Doubling Interlace Even Scan Only
Note 1. Line doubling option is not supported with dual panel. 2. Dual Panel Considerations When configured for a dual panel LCD and using Simultaneous Display, the Half Frame Buffer Disable, REG[1Bh] bit 0, must be set to 1. This will result in a lower contrast on the LCD panel, which then may require adjustment. Normal - the image is the same on both displays, i.e. 640x240. CRT parameters determine the LCD image. The LCD image will appear to be washed out due to the 1/525 duty cycle of the CRT. Line Doubling - each line is sent to the CRT twice, giving a 640x480 image which has a long aspect ratio. The image on the LCD has each line sent twice but only one FPLINE. This gives a duty cycle of 2/525, which is very close to the LCD only mode duty cycle of 1/242, so the image on the LCD will have almost the same contrast as that of a single LCD. Interlace - odd frames receive odd scan lines and even frames receive even scan lines. The 640x480 image on the CRT will be normal while the image on the 640x240 LCD will appear to be squashed, though text will be readable. Even Scan Only - the 640x480 image on the CRT is normal. The LCD (640x240) only receives the even scan lines. The image on the LCD does not flicker, but it may be hard to read text.
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bits 4-2
Number of Bits-Per-Pixel Select Bits [2:0] These bits select the number of bits-per-pixel (bpp) for the displayed data. Note 15 and 16-bpp modes bypass the LUT and are supported as 12-bpp on passive panels and 15/16bpp on TFT panels. These modes are not supported on CRT. See Figure 10-2: "15/16 Bit-PerPixel Format Memory Organization," on page 116 for a description of passive panel support.
Table 8-7: Number of Bits-Per-Pixel Selection Number Of Bits-Per-Pixel Select Bits [2:0] 000 001 010 011 100 101 110-111 Number of Bits-Per-Pixel 1 2 4 8 15 16 Reserved
bit 1
CRT Enable This bit enables the CRT control signals. Note REG[02h] bit 1 must = 0 when in CRT only mode.
bit 0
LCD Enable This bit enables the LCD control signals. Programming this bit from a 0 to a 1 starts the LCD power-on sequence. Programming this bit from a 1 to a 0 starts the LCD power-off sequence.
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Screen 1 Line Compare Register 0
REG[0Eh] RW Screen 1 Line Screen 1 Line Screen 1 Line Screen 1 Line Screen 1 Line Screen 1 Line Screen 1 Line Screen 1 Line Compare Bit 7 Compare Bit 6 Compare Bit 5 Compare Bit 4 Compare Bit 3 Compare Bit 2 Compare Bit 1 Compare Bit 0
Screen 1 Line Compare Register 1
REG[0Fh] n/a n/a n/a n/a n/a n/a RW Screen 1 Line Screen 1 Line Compare Bit 9 Compare Bit 8
REG[0Eh] bits 7-0 REG[0Fh] bits 1-0
Screen 1 Line Compare Bits [9:0] In split screen mode, the panel is divided into screen 1 and screen 2, with screen 1 above screen 2. These registers form a 10-bit value that specify the screen 1 size in 1-line resolution. The maximum screen 1 vertical size is 1024 lines. Screen 2 is visible only if the screen 1 line compare is less than the vertical panel size. The starting address for screen 1 is given by the Screen 1 Display Start Address registers (REG[10h], REG[11h], REG[12h]). The starting address for screen 2 is given by the Screen 2 Display Start Address registers (REG[13h], REG[14h], REG[15h]). For normal operation (no split screen): this register must be set greater than the vertical display height REG[08h] and REG[09h] (e.g. set to 3FFh). For split screen on a single panel: Split screen 1 vertical size in number of lines = (ContentsOfThisRegister) + 1 For split screen on a dual panel: Split screen 1 vertical size in number of lines = (ContentsOfThisRegister) + 1, if (ContentsOfThisRegister) 00EFh or Split screen 1 vertical size in number of lines = (ContentsOfThisRegister) + 2, if (ContentsOfThisRegister) > 00EFh Note For further details, see Section 10.2, "Image Manipulation" on page 117 and the S1D13504 Programming Notes and Examples, document number X19A-G-002-xx.
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Screen 1 Display Start Address Register 0
REG[10h] RW Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Screen 1 Display Start Address Register 1
REG[11h] RW Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Screen 1 Display Start Address Register 2
REG[12h] n/a n/a n/a n/a RW Start Address Start Address Start Address Start Address Bit 19 Bit 18 Bit 17 Bit 16
REG[10h] bits 7-0 REG[11h] bits 7-0 REG[12h] bits 3-0
Screen 1 Start Address Bits [19:0] This register forms the 20-bit address for the starting word of the screen 1 image in the display buffer. Note that this is a word address. An entry of 0000h into these registers represents the first word of display memory, an entry of 0001h represents the second word of display memory, and so on. See Section 10, "Display Configuration" on page 115 for details.
Screen 2 Display Start Address Register 0 RW
REG[13h] RW Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Screen 2 Display Start Address Register 1
REG[14h] RW Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Screen 2 Display Start Address Register 2
REG[15h] n/a n/a n/a n/a RW Start Address Start Address Start Address Start Address Bit 19 Bit 18 Bit 17 Bit 16
REG[13h] bits 7-0 REG[14h] bits 7-0 REG[15h] bits 3-0
Screen 2 Start Address Bits [19:0] This register forms the 20-bit address for the starting word of the screen 2 image in the display buffer. Note that this is a word address. An entry of 0000h into these registers represents the first word of display memory, an entry of 0001h represents the second word of display memory, and so on. See Section 10, "Display Configuration" on page 115 for details.
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Memory Address Offset Register 0
REG[16h] Memory Address Offset Bit 7 Memory Address Offset Bit 6 Memory Address Offset Bit 5 Memory Address Offset Bit 4 Memory Address Offset Bit 3 Memory Address Offset Bit 2 Memory Address Offset Bit 1 RW Memory Address Offset Bit 0
Memory Address Offset Register 1
REG[17h] n/a n/a n/a n/a n/a n/a Memory Address Offset Bit 9 RW Memory Address Offset Bit 8
REG[16] bits 7-0 REG[17] bits 1-0
Memory Address Offset Bits [9:0] These bits are the 10-bit address offset from the starting word of line "n" to the starting word of line "n + 1". This value is applied to both screen 1 and screen 2. Note This value is in words and must be programmed REG[04h]. A virtual image can be formed by setting this register to a value greater than the width of the display. The displayed image is a window into the larger virtual image. See Section 10, "Display Configuration" on page 115 for details.
b
Pixel Panning Register
REG[18h] RW Screen 2 Screen 2 Screen 2 Screen 1 Screen 1 Screen 1 Screen 1 Screen 2 Pixel Panning Pixel Panning Pixel Panning Pixel Panning Pixel Panning Pixel Panning Pixel Panning Pixel Panning Bit 3 Bit 2 Bit 1 Bit 0 Bit 3 Bit 2 Bit 1 Bit 0
This register is used to control the horizontal pixel panning of screen 1 and screen 2. Each screen can be independently panned to the left by programming its respective Pixel Panning Bits to a nonzero value. This value represents the number of pixels panned. The maximum pan value is dependent on the display mode as shown in the table below.
Table 8-8: Pixel Panning Selection Number of Bits-Per-Pixel 1 2 4 8 15/16 Screen 2 Pixel Panning Bits Used Bits [3:0] Bits [2:0] Bits [1:0] Bit 0 ---
Smooth horizontal panning can be achieved by a combination of this register and the Display Start Address register. See Section 10, "Display Configuration" on page 115 and S1D13504 Programming Notes and Examples, document number X19A-G-002-xx, Section 4 for details. bits 7-4 bits 3-0 Screen 2 Pixel Panning Bits [3:0] Pixel panning bits for screen 2. Screen 1 Pixel Panning Bits [3:0] Pixel panning bits for screen 1.
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8.2.5 Clock Configuration Register
Clock Configuration Register
REG[19h] n/a n/a n/a n/a n/a MCLK Divide Select PCLK Divide Select Bit 1 RW PCLK Divide Select Bit 0
bit 2
MCLK Divide Select When this bit = 1 the memory clock (MCLK) frequency is half of the input clock frequency. When this bit = 0 the memory clock frequency is equal to the input clock frequency. PCLK Divide Select Bits [1:0] These bits determine the amount of divide from the memory clock to generate the pixel clock (PCLK):
Table 8-9: PCLK Divide Selection PCLK Divide Select Bits [1:0] 00 01 10 11 MCLK/PCLK Frequency Ratio 1 2 3 4
bits 1-0
See Section 11.2, "Frame Rate Calculation" on page 119 for selection of PCLK frequency.
8.2.6 Power Save Configuration Registers
Power Save Configuration Register
REG[1Ah] n/a n/a n/a n/a LCD Power Disable Suspend Refresh Select Bit 1 Suspend Refresh Select Bit 0 RW Software Suspend Mode Enable
bit 3
LCD Power Disable When this bit = 1 the LCDPWR output is directly forced to the Off state. The LCDPWR "On/Off" state is configured by MD10 at the rising edge of RESET#. When this bit = 0 the LCDPWR output is controlled by the panel on/off sequencing logic. See Table 5-8: "Summary of Power On / Reset Options," on page 30. Suspend Refresh Select Bits [1:0] These bits specify the type of DRAM refresh to use in Suspend mode.
Table 8-10: Suspend Refresh Selection Suspend Refresh Select Bits [1:0] 00 01 1x DRAM Refresh Type CBR Refresh Self-Refresh No Refresh
bits 2-1
Note These bits should not be changed when suspend mode is enabled. bit 0 Software Suspend Mode Enable When this bit = 1 software suspend mode is enabled. When this bit = 0 software suspend mode is disabled.
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8.2.7 Miscellaneous Registers
Miscellaneous Disable Register
REG[1Bh] Host Interface n/a Disable n/a n/a n/a n/a n/a RW Half Frame Buffer Disable
bit 7
Host Interface Disable This bit must be programmed to 0 to enable the Host Interface. This bit goes high on reset. When this bit is high, all memory and all registers except REG[1Ah] (read-only), REG[28h] through REG[2Fh], and REG[1Bh] are inaccessible. Half Frame Buffer Disable This bit is used to disable the Half Frame Buffer. When this bit = 1, the Half Frame Buffer is disabled. When this bit = 0, the Half Frame Buffer is enabled. When a single panel is selected, the Half Frame Buffer is automatically disabled and this bit has no hardware effect. The Half Frame Buffer is needed to fully support dual panels. Disabling the Half Frame Buffer reduces memory bandwidth requirements and increases the supportable pixel clock frequency, but results in reduced contrast on the LCD panel. This mode is not normally used except in special circumstances such as simultaneous display on a CRT and dual panel LCD. See Section 11.2 on page 119 for details. Note The Half Frame Buffer should be disabled only when idle. The Half Frame Buffer is idle during vertical non-display periods (i.e. when REG[0Ah] bit 7 = 1), or while in suspend mode. For programming information, see S1D13504 Programming Notes and Examples, document number X19A-G-002-xx.
bit 0
MD Configuration Readback Register 0
REG[1Ch] MD7 Status MD6 Status MD5 Status MD4 Status MD3 Status MD2 Status MD1 Status RO MD0 Status
MD Configuration Readback Register 1
REG[1Dh] MD15 Status MD14 Status MD13 Status MD12 Status MD11 Status MD10 Status MD9 Status MD8 Status RO
REG[1Ch] bits 7-0 REG[1Dh] bits 7-0
MD[15:0] Configuration Status These are read-only status bits for the MD[15:0] pins configuration status at the rising edge of RESET#. See Table 5-8: "Summary of Power On / Reset Options," on page 30.
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GPIO Configuration Register 0
REG[1Eh] GPIO7 Pin IO Config. GPIO6 Pin IO Config. GPIO5 Pin IO Config. GPIO4 Pin IO Config. GPIO3 Pin IO Config. GPIO2 Pin IO Config. GPIO1 Pin IO Config. RW GPIO0 Pin IO Config.
bit 7
GPIO7 Pin IO Configuration When this bit = 1, GPIO7 is configured as an output. When this bit = 0 (default), GPIO7 is configured as an input. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO7, otherwise the DACWR# pin is controlled automatically and this bit will have no effect on hardware. GPIO6 Pin IO Configuration When this bit = 1, GPIO6 is configured as an output. When this bit = 0 (default), GPIO6 is configured as an input. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO6, otherwise the DACP0 pin is controlled automatically and this bit will have no effect on hardware. GPIO5 Pin IO Configuration When this bit = 1, GPIO5 is configured as an output. When this bit = 0 (default), GPIO5 is configured as an input. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO5, otherwise the BLANK# pin is controlled automatically and this bit will have no effect on hardware. GPIO4 Pin IO Configuration When this bit = 1, GPIO4 is configured as an output. When this bit = 0 (default), GPIO4 is configured as an input. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO4, otherwise the DACRD# pin is controlled automatically and this bit will have no effect on hardware. GPIO3 Pin IO Configuration When this bit = 1, GPIO3 is configured as an output. When this bit = 0 (default), GPIO3 is configured as an input. Note the MD[7:6] pins must be properly configured at the rising edge of RESET# to enable GPIO3, otherwise the MA9 pin is controlled automatically and this bit will have no effect on hardware. GPIO2 Pin IO Configuration When this bit = 1, GPIO2 is configured as an output. When this bit = 0 (default), GPIO2 is configured as an input. Note the MD[7:6] pins must be properly configured at the rising edge of RESET# to enable GPIO2, otherwise the MA11 pin is controlled automatically and this bit will have no effect on hardware. GPIO1 Pin IO Configuration When this bit = 1, GPIO1 is configured as an output. When this bit = 0 (default), GPIO1 is configured as an input. Note the MD[7:6] pins must be properly configured at the rising edge of RESET# to enable GPIO1, otherwise the MA10 pin is controlled automatically and this bit will have no effect on hardware. GPIO0 Pin IO Configuration When this bit = 1, GPIO0 is configured as an output. When this bit = 0 (default), GPIO0 is configured as an input.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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GPIO Configuration Register 1
REG[1Fh] n/a n/a n/a n/a GPIO11 Pin IO Config. GPIO10 Pin IO Config. GPIO9 Pin IO Config. RW GPIO8 Pin IO Config.
bit 3
GPIO11 Pin IO Configuration When this bit = 1, GPIO11 is configured as an output. When this bit = 0 (default), GPIO11 is configured as an input. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO11, otherwise the VRTC pin is controlled automatically and this bit will have no effect on hardware. GPIO10 Pin IO Configuration When this bit = 1, GPIO10 is configured as an output. When this bit = 0 (default), GPIO10 is configured as an input. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO10, otherwise the HRTC pin is controlled automatically and this bit will have no effect on hardware. GPIO9 Pin IO Configuration When this bit = 1, GPIO9 is configured as an output. When this bit = 0 (default), GPIO9 is configured as an input. Note GPIO9 and GPIO8 must always be set to the same function (both to input or both to output). The MD8 pin must be high at the rising edge of RESET# to enable GPIO9, otherwise the DACRS1 pin is controlled automatically and this bit will have no effect on hardware.
bit 2
bit 1
bit 0
GPIO8 Pin IO Configuration When this bit = 1, GPIO8 is configured as an output. When this bit = 0 (default), GPIO8 is configured as an input. Note GPIO8 and GPIO9 must always be set to the same function (both to input or both to output). The MD8 pin must be high at the rising edge of RESET# to enable GPIO8, otherwise the DACRS0 pin is controlled automatically and this bit will have no effect on hardware.
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GPIO Status / Control Register 0
REG[20h] GPIO7 Pin IO Status GPIO6 Pin IO Status GPIO5 Pin IO Status GPIO4 Pin IO Status GPIO3 Pin IO Status GPIO2 Pin IO Status GPIO1 Pin IO Status RW GPIO0 Pin IO Status
bit 7
GPIO7 Pin IO Status When GPIO7 is configured as an output, a "1" in this bit drives GPIO7 to high and a "0" in this bit drives GPIO7 to low. When GPIO7 is configured as an input, a read from this bit returns the status of GPIO7. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO7, otherwise the DACWR# pin is controlled automatically and this bit will have no effect on hardware. GPIO6 Pin IO Status When GPIO6 is configured as an output, a "1" in this bit drives GPIO6 to high and a "0" in this bit drives GPIO6 to low. When GPIO6 is configured as an input, a read from this bit returns the status of GPIO6. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO6, otherwise the DACP0 pin is controlled automatically and this bit will have no effect on hardware. GPIO5 Pin IO Status When GPIO5 is configured as an output, a "1" in this bit drives GPIO5 to high and a "0" in this bit drives GPIO5 to low. When GPIO5 is configured as an input, a read from this bit returns the status of GPIO5. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO5, otherwise the BLANK# pin is controlled automatically and this bit will have no effect on hardware. GPIO4 Pin IO Status When GPIO4 is configured as an output, a "1" in this bit drives GPIO4 to high and a "0" in this bit drives GPIO4 to low. When GPIO4 is configured as an input, a read from this bit returns the status of GPIO4. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO4, otherwise the DACRD# pin is controlled automatically and this bit will have no effect on hardware. GPIO3 Pin IO Status When GPIO3 is configured as an output, a "1" in this bit drives GPIO3 to high and a "0" in this bit drives GPIO3 to low. When GPIO3 is configured as an input, a read from this bit returns the status of GPIO3. Note the MD[7:6] pins must be properly configured at the rising edge of RESET# to enable GPIO3, otherwise the MA9 pin is controlled automatically and this bit will have no effect on hardware. GPIO2 Pin IO Status When GPIO2 is configured as an output, a "1" in this bit drives GPIO2 to high and a "0" in this bit drives GPIO2 to low. When GPIO2 is configured as an input, a read from this bit returns the status of GPIO2. Note the MD[7:6] pins must be properly configured at the rising edge of RESET# to enable GPIO2, otherwise the MA11 pin is controlled automatically and this bit will have no effect on hardware. GPIO1 Pin IO Status When GPIO1 is configured as an output, a "1" in this bit drives GPIO1 to high and a "0" in this bit drives GPIO1 to low. When GPIO1 is configured as an input, a read from this bit returns the status of GPIO1. Note the MD[7:6] pins must be properly configured at the rising edge of RESET# to enable GPIO1, otherwise the MA10 pin is controlled automatically and this bit will have no effect on hardware. GPIO0 Pin IO Status When GPIO0 is configured as an output, a "1" in this bit drives GPIO0 to high and a "0" in this bit drives GPIO0 to low. When GPIO0 is configured as an input, a read from this bit returns the status of GPIO0.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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GPIO Status / Control Register 1
REG[21h] GPO Control n/a n/a n/a GPIO11 Pin IO Status GPIO10 Pin IO Status GPIO9 Pin IO Status RW GPIO8 Pin IO Status
bit 7
GPO Control This bit is used to control the state of the SUSPEND# pin when it is configured as GPO. The SUSPEND# pin can be used as a power-down input (SUSPEND#) or as an output (GPO) possibly used for controlling the LCD backlight power: * When MD9 = 0 at rising edge of RESET#, SUSPEND# is an active-low Schmitt input used to put the S1D13504 into suspend mode - see Section 13, "Power Save Modes" on page 127 for details. * When MD[10:9] = 01 at rising edge of RESET#, SUSPEND# is an output with a reset state of 1. * When MD[10:9] = 11 at rising edge of RESET#, SUSPEND# is an output with a reset state of 0. When this bit = 0 the GPO output is set to the reset state. When this bit = 1 the GPO output pin is set to the inverse of the reset state.
bit 3
GPIO11 Pin IO Status When GPIO11 is configured as an output, a "1" in this bit drives GPIO11 to high and a "0" in this bit drives GPIO11 to low. When GPIO11 is configured as an input, a read from this bit returns the status of GPIO11. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO11, otherwise the VRTC pin is controlled automatically and this bit will have no effect on hardware. GPIO10 Pin IO Status When GPIO10 is configured as an output, a "1" in this bit drives GPIO10 to high and a "0" in this bit drives GPIO10 to low. When GPIO10 is configured as an input, a read from this bit returns the status of GPIO10. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO10, otherwise the HRTC pin is controlled automatically and this bit will have no effect on hardware. GPIO9 Pin IO Status When GPIO9 is configured as an output, a "1" in this bit drives GPIO9 to high and a "0" in this bit drives GPIO9 to low. When GPIO9 is configured as an input, a read from this bit returns the status of GPIO9. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO9, otherwise the DACRS1 pin is controlled automatically and this bit will have no effect on hardware. GPIO8 Pin IO Status When GPIO8 is configured as an output, a "1" in this bit drives GPIO8 to high and a "0" in this bit drives GPIO8 to low. When GPIO8 is configured as an input, a read from this bit returns the status of GPIO8. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO8, otherwise the DACRS0 pin is controlled automatically and this bit will have no effect on hardware.
bit 2
bit 1
bit 0
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Performance Enhancement Register 0
REG[22h] EDO ReadWrite Delay RC Timing Value Bit 1 RC Timing Value Bit 0 RAS# to CAS# Delay RAS# Precharge Timing Bit 1 RAS# Precharge Timing Bit 0 n/a RW Reserved
Note Changing this register to non-zero value, or to a different non-zero value, should be done only when there are no read/write DRAM cycles. This condition occurs when both the Display FIFO is disabled (REG[23h] bit 7 = 1) and the Half Frame Buffer is disabled (REG[1Bh] bit 0 = 1). For programming information, see S1D13504 Programming Notes and Examples, document number X19A-G-002-xx. bit 7 EDO Read-Write Delay This bit is used for EDO-DRAM to select the delay during the read-write transition. A "0" selects 2 MCLK delay for the read-write transition. A "1" selects 1 MCLK delay for the read-write DRAM. This bit has no effect for FPM-DRAM which always uses 1 MCLK delay for the read-write transition. This bit may be programmed to 1 when the MCLK frequency is less than 30MHz. RC Timing Value (NRC) Bits [1:0] These bits select the DRAM random-cycle timing parameter, tRC. These bits specify the number (NRC) of MCLK periods (TM) used to create tRC. NRC should be chosen to meet tRC as well as tRAS, the RAS pulse width. Use the following two formulae to calculate NRC then choose the larger value. Note, these formulae assume an MCLK duty cycle of 50 +/- 5%. NRC NRC = Round-Up (tRC/TM) = Round-Up (tRAS/TM + NRP) = Round-Up (tRAS/TM + 1.55) = (NRC) TM
Table 8-11: Minimum Memory Timing Selection REG[22h] Bits [6:5] 00 01 10 11 NRC 5 4 3 Reserved Minimum Random Cycle Width (tRC) 5 TM 4 TM 3 TM Reserved
bits 6-5
if NRP = 1 or 2 if NRP = 1.5
The resulting tRC is related to NRC as follows: tRC
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bit 4
RAS# to CAS# Delay (NRCD) This bit selects the DRAM RAS# to CAS# delay parameter, tRCD. This bit specifies the number (NRCD) of MCLK periods (TM) used to create tRCD. NRCD must be chosen to satisfy the RAS# access time, tRAC. Note, these formulae assume an MCLK duty cycle of 50 +/- 5%. NRCD = Round-Up((tRAC + 5)/TM - 1) =2 = Round-Up(tRAC/TM - 1) = Round-Up(tRAC/TM - 0.45) if EDO and NRP = 1 or 2 if EDO and NRP = 1.5 if FPM and NRP = 1 or 2 if FPM and NRP = 1.5
Note that for EDO-DRAM and NRP = 1.5, this bit is automatically forced to 0 to select 2 MCLK for NRCD. This is done to satisfy the CAS# address setup time, tASC. The resulting tRC is related to NRCD as follows: tRC tRC tRC tRC = (NRCD) TM = (1.5) TM = (NRCD + 0.5) TM = (NRCD) TM if EDO and NRP = 1 or 2 if EDO and NRP = 1.5 if FPM and NRP = 1 or 2 if FPM and NRP = 1.5
Table 8-12: RAS-to-CAS Delay Timing Select REG[22h] Bit 4 0 1 NRCD 2 1 RAS# to CAS# Delay (tRCD) 2 TM 1 TM
bits 3-2
RAS# Precharge Timing (NRP) Bits [1:0] Minimum Memory Timing for RAS precharge These bits select the DRAM RAS# Precharge timing parameter, tRP. These bits specify the number (NRP) of MCLK periods (TM) used to create tRP - see the following formulae. Note, these formulae assume an MCLK duty cycle of 50 +/- 5%. NRP =1 = 1.5 =2 if (tRP/TM) < 1 if 1 (tRP/TM) < 1.45 if (tRP/TM) 1.45 if FPM refresh cycle and NRP = 1 or 2 for all other
The resulting tRC is related to NRP as follows: tRC tRC = (NRP + 0.5) TM = (NRP) TM
Table 8-13: RAS Precharge Timing Select REG[22h] Bits [3:2] 00 01 10 11 NRP 2 1.5 1 Reserved RAS# Precharge Width (tRP) 2 TM 1.5 TM 1 TM Reserved
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Optimal DRAM Timing The following table contains the optimally programmed values of NRC, NRP, and NRCD for different DRAM types, at maximum MCLK frequencies.
Table 8-14: Optimal NRC, NRP, and NRCD Values at Maximum MCLK Frequency DRAM Type EDO FPM DRAM Speed
(ns)
TM (ns) 25 30 33 40 50
NRC (#MCLK) 4 4 5 4 3
NRP (#MCLK) 1.5 1.5 2 1.5 1.5
NRCD (#MCLK) 2 2 2 2 1
50 60 70 60 70
bit 0
Reserved Must be set to 0.
Performance Enhancement Register 1
REG[23h] Display FIFO Disable n/a n/a Display FIFO Threshold Bit 4 Display FIFO Threshold Bit 3 Display FIFO Threshold Bit 2 Display FIFO Threshold Bit 1 Display FIFO Threshold Bit 0
bit 7
Display FIFO Disable When this bit = 1 the display FIFO is disabled and all data outputs are forced to zero (i.e. the screen is blanked). This allows the S1D13504 to be dedicated to service CPU to memory accesses. When this bit = 0 the display FIFO is enabled. Display FIFO Threshold Bits [4:0] These bits should be set to a value of 10h upon initialization as this provides the best overall performance for all display modes.
bits 4-0
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8.2.8 Look-Up Table Registers
The S1D13504 has three internal 16 position, 4-bit wide Look-Up Tables. The 4-bit value programmed into each table position determines the color weighting of display data; the output gray shade is derived from the Green Look-Up Table. These tables are bypassed in 15/16-bpp mode. These three 16 position Look-Up Tables can be arranged in many different configurations to accommodate all the gray shade / color display modes. Look-Up Table Address Register
REG[24h] n/a n/a RGB Index Bit 1 RGB Index Bit 0 LUT Address Bit 3 LUT Address Bit 2 LUT Address Bit 1 RW LUT Address Bit 0
bits 5-4
RGB Index Bits [1:0] These bits are also used to provide access to the three internal Look-Up Tables (RGB).
Table 8-15: RGB Index Selection RGB Index Bits [1:0] 00 01 10 11 Look-Up Table Access Auto-Increment R, G, B LUT Auto-Increment Red LUT only Auto-Increment Green LUT only Auto-Increment Blue LUT only Pointer Sequence R[n], G[n], B[n], R[n+1], G[n+1] . . . R[n], R[n+1], R[n+2] . . . G[n], G[n+1], G[n+2] . . . B[n], B[n+1], B[n+2] . . .
A write to this register with RGB Index bits = 00 selected will position the internal pointer to the Red LUT. Each read/write access to the LUT data will increment the counter to point to the next LUT in order (R to G to B to R...). A read/write access to the Blue LUT will also automatically increment the LUT address by 1. This provides an efficient method for sequential writing of RGB data. When the RGB Index bits = 01, 10, or 11, the internal pointer always points to the respective R, G, or B LUT. A read/write access to the LUT data will increment the LUT address by 1. bits 3-0 LUT Address Bits [3:0] These 4 bits provide a pointer into the 16 position Look-Up Table currently selected for CPU read/write access. The Look-Up Table configuration (e.g. 1/2/4 banks) does not affect the read/write access from the CPU as all 16 positions can be accessed sequentially. Look-Up Table Data Register
REG[26h] n/a n/a n/a n/a LUT Data Bit 3 LUT Data Bit 2 LUT Data Bit 1 RW LUT Data Bit 0
bits 3-0
LUT Data Bits [3:0] These 4 bits are the gray shade/color values used for display data output. They are programmed into the 4-bit Look-Up Table positions pointed to by LUT Address bits [3:0] and RGB Index bits [1:0] (if in color display modes). For example: in a 16-level gray shade display mode, a data value of 0001b (4 bits-per-pixel) will point to Look-Up Table position one and display the 4-bit gray shade corresponding to the value programmed into that location.
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Look-Up Table Bank Select Register
REG[27h] n/a n/a Red Bank Select Bit 1 Red Bank Select Bit 0 Blue Bank Select Bit 1 Blue Bank Select Bit 0 Green Bank Select Bit 1 RW Green Bank Select Bit 0
bit 5-4
Red Bank Select Bits [1:0] In 2-bpp mode, the 16 position Red LUT is arranged into four, 4 position "banks." These two bits control which bank is currently selected. In 8-bpp mode, the 16 position Red LUT is arranged into two, 8 position "banks." Only bit 0 of these two bits controls which bank is currently selected. These bits have no effect in 1-bpp, 4-bpp, 15/16-bpp mode, or all monochrome modes.
bit 3-2
Blue Bank Select Bits [1:0] In both 2-bpp and 8-bpp modes, the 16 position Blue LUT is arranged into four 4 position "banks." These two bits control which bank is currently selected. These bits have no effect in 1-bpp, 4-bpp, 15/16-bpp mode, or all monochrome modes.
bits 1-0
Green Bank Select Bits [1:0] In 2-bpp mode, the 16 position Green LUT is arranged into four, 4 position "banks." These two bits control which bank is currently selected. In 8-bpp mode, the 16 position Green LUT is arranged into two, 8 position "banks." Only bit 0 of these two bits controls which bank is currently selected. These bits have no effect in 1-bpp, 4-bpp, and 15/16-bpp modes.
8.2.9 External RAMDAC Control Registers
Note 1. In a Little-Endian architecture, the RAMDAC should be connected to the low byte of the CPU data bus and the following registers are accessed at the lower address given for each register (28h, 2Ah, 2Ch, and 2Eh). In a Big-Endian architecture, the RAMDAC should be connected to the high byte of the CPU data bus and the following registers are accessed at the higher address given for each register (29h, 2Bh, 2Dh, and 2Fh). 2. When accessing the External RAMDAC Control registers with either of the architectures described in note 1, accessing the adjacent unused registers is prohibited. 3. To access the RAMDAC registers the CRT enable bit, REG[0Dh] bit 1, must be set to 1.
RAMDAC Pixel Read Mask Register
REG[28h] or REG[29h] RAMDAC Data Bit 7 RAMDAC Data Bit 6 RAMDAC Data Bit 5 RAMDAC Data Bit 4 RAMDAC Data Bit 3 RAMDAC Data Bit 2 RAMDAC Data Bit 1 RW RAMDAC Data Bit 0
bits 7-0
RAMDAC Pixel Read Mask Bits [7:0] A CPU read or write to this register will generate a DACRD# or DACWR# pulse and DACRS1 = 1 and DACRS0 = 0 to the external RAMDAC for a pixel read mask register access. The RAMDAC data must be transferred directly between the system data bus and the external RAMDAC through either data bus bits [7:0] in a Little-Endian system or data bus bits [15:8] in a Big-Endian system.
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RAMDAC Read Mode Address Register
REG[2Ah] or REG[2Bh] RAMDAC Address Bit 7 RAMDAC Address Bit 6 RAMDAC Address Bit 5 RAMDAC Address Bit 4 RAMDAC Address Bit 3 RAMDAC Address Bit 2 RAMDAC Address Bit 1 RW RAMDAC Address Bit 0
bits 7-0
RAMDAC Read Mode Address Bits [7:0] A CPU read or write to this register will generate a DACRD# or DACWR# pulse and DACRS1 = 1 and DACRS0 = 1 to the external RAMDAC for a read-mode address register access. The RAMDAC address must be transferred directly between the system data bus and the external RAMDAC through either data bus bits [7:0] in a Little-Endian system or data bus bits [15:8] in a Big-Endian system.
RAMDAC Write Mode Address Register
REG[2Ch] or REG[2Dh] RAMDAC Address Bit 7 RAMDAC Address Bit 6 RAMDAC Address Bit 5 RAMDAC Address Bit 4 RAMDAC Address Bit 3 RAMDAC Address Bit 2 RAMDAC Address Bit 1 RW RAMDAC Address Bit 0
bits 7-0
RAMDAC Write Mode Address Bits [7:0] A CPU read or write to this register will generate a DACRD# or DACWR# pulse and DACRS1 = 0 and DACRS0 = 0 to the external RAMDAC for a write-mode address register access. The RAMDAC address must be transferred directly between the system data bus and the external RAMDAC through either data bus bits [7:0] in a Little-Endian system or data bus bits [15:8] in a Big-Endian system.
RAMDAC Palette Data Register
REG[2Eh] or REG[2Fh] RAMDAC Data Bit 7 RAMDAC Data Bit 6 RAMDAC Data Bit 5 RAMDAC Data Bit 4 RAMDAC Data Bit 3 RAMDAC Data Bit 2 RAMDAC Data Bit 1 RW RAMDAC Data Bit 0
bits 7-0
RAMDAC Palette Data Bits [7:0] A CPU read or write to this register will generate a DACRD# or DACWR# pulse and DACRS1 = 0 and DACRS0 = 1 to the external RAMDAC for a palette data register access. The RAMDAC data must be transferred directly between the system data bus and the external RAMDAC through either data bus bits [7:0] in a Little-Endian system or data bus bits [15:8] in a Big-Endian system.
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9 Display Buffer
The system addresses the display buffer through the CS#, M/R#, and AB[20:0] input pins. When CS# = 0 and M/R# = 1, the display buffer is addressed by bits AB[20:0] as shown in the following table.
Table 9-1: S1D13504 Addressing CS# M/R# Register access: 0 0 * REG[00h] is addressed when AB[5:0] = 0 * REG[01h] is addressed when AB[5:0] = 1 * REG[n] is addressed when AB[5:0] = n Memory access: the 2M byte display buffer is addressed by AB[20:0] S1D13504 not selected Access
0 1
1 X
The display buffer address space is always 2M bytes. However, the physical display buffer may be either 512K bytes or 2M bytes. See Section 5.5, "Summary of Configuration Options" on page 30. The 512K byte display buffer is replicated in the 2M byte address space as shown below.
512K byte Memory
AB[20:0] 000000h
2M byte Memory
Image Buffer Half-Frame Buffer Image Buffer Half-Frame Buffer Image Buffer Half-Frame Buffer Image Buffer Half-Frame Buffer Half-Frame Buffer 17FFFFh 180000h 0FFFFFh 100000h Image Buffer 07FFFFh 080000h
1FFFFFh
Figure 9-1: Display Buffer Addressing
The display buffer will contain an image buffer and may also contain a half-frame buffer.
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9.1 Image Buffer
The image buffer contains the formatted display data - see Section 10.1, "Display Mode Data Format" on page 115. The displayed image(s) may take up only a portion of the image buffer; the remaining area can be used for multiple images - possibly for animation or general storage. See Section 10, "Display Configuration" on page 115 for details on the relationship between the image buffer and the display.
9.2 Half Frame Buffer
In dual panel mode, with the half frame buffer enabled, the top of the display buffer is allocated to the half-frame buffer. The size of the half frame buffer is a function of the panel resolution and whether the panel is color or monochrome: Half Frame Buffer Size (in bytes) = (panel width x panel length) * factor / 16 where factor = 4 for color panel = 1 for monochrome panel For example, for a 640x480 8 bpp color panel the half frame buffer size is 75K bytes. In a 512K byte display buffer, the half-frame buffer resides from 6D400h to 7FFFFh. In a 2M byte display buffer, the half-frame buffer resides from 1ED400h to 1FFFFFh.
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10 Display Configuration
10.1 Display Mode Data Format
1-bpp: Byte 0
bit 7 A0 A1 A2 A3 A4 A5 A6
bit 0 A7
P0 P1 P2 P3 P4 P5 P6 P7
Pn = (An)
Panel Display Host Address Display Buffer
2-bpp: Byte 0 Byte 1
bit 7 A0 A4 B0 B4 A1 A5 B1 B5 A2 A6 B2 B6 A3 A7
bit 0 B3 B7
P0 P1 P2 P3 P4 P5 P6 P7
Pn = (An, Bn) Panel Display
Host Address
Display Buffer
4-bpp: bit 7 Byte 0 Byte 1 Byte 2 A0 A2 A4 B0 B2 B4 C0 C2 C4 D0 D2 D4 A1 A3 A5 B1 B3 B5 C1 C3 C5 bit 0 D1 D3 D5 Pn = (An, Bn, Cn, Dn) P0 P1 P2 P3 P4 P5 P6 P7
Panel Display Host Address Display Buffer
8-bpp: bit 7 Byte 0 Byte 1 Byte 2 R0
2
3-3-2 RGB bit 0
1 R01 R00 G02 G01 G00 B0 B00
P0 P1 P2 P3 P4 P5 P6 P7
1 R12 R11 R10 G12 G11 G10 B1 B10 1 R22 R21 R20 G22 G21 G20 B2 B20
Pn = (Rn2-0, Gn 2-0, Bn1-0)
Panel Display Host Address Display Buffer
Figure 10-1: 1/2/4/8 Bit-Per-Pixel Format Memory Organization
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15-bpp: 5-5-5 RGB bit 7 Byte 0 Byte 1 Byte 2 Byte 3 bit 0 G02 G01 G00 B04 B03 B02 B01 B00 R0
4
P0 P1 P2 P3 P4 P5 P6 P7
R03 R0
2
R0
1
R0
0
G04
G0
3
TFT Pn = (Rn4-0, Gn 4-0, Bn4-0) Passive Pn = (Rn4-1, Gn 4-1, Bn4-1) Panel Display
G12 G11 G10 B14 B13 B12 B11 B10
4 R14 R13 R12 R11 R10 G1 G13
Host Address
Display Buffer
16-bpp: 5-6-5 RGB bit 7 Byte 0 Byte 1 Byte 2 Byte 3 bit 0 TFT Pn = (Rn4-0, Gn 5-0, Bn4-0) Passive Pn = (Rn4-1, Gn 5-2, Bn4-1) Panel Display G02 G01 G00 B04 B03 B02 B01 B00 R04 R03 R02 R01 R00 G05 G04 G03 G12 G11 G10 B14 B13 B12 B11 B10 R14 R13 R12 R11 R10 G15 G14 G13 P0 P1 P2 P3 P4 P5 P6 P7
Host Address
Display Buffer
Figure 10-2: 15/16 Bit-Per-Pixel Format Memory Organization
Note 1. The Host-to-Display mapping described here assumes that a Little-Endian interface is being used. 2. For 8/15/16 bit-per-pixel formats, Rn, Gn, Bn represent the red, green, and blue color components.
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10.2 Image Manipulation
The figure below shows how screen 1 and screen 2 images stored in the image buffer are positioned on the display. The screen 1 and screen 2 images can be parts of a larger virtual image or images. * (REG[17h], REG[16h]) defines the width of the virtual image(s). * (REG[12h], REG[11h], REG[10h]) defines the starting word of the screen 1, (REG[15h], REG[14h], REG[13h]) defines the starting word of the screen 2. * REG[18h] bits [3:0] define the starting pixel within the starting word for screen 1, REG[18h] bits[7:4] define the starting pixel within the starting word for screen 2. * (REG[0Fh],REG[0Eh]) define the last line of screen 1, the remainder of the display is taken up by screen 2. Image Buffer
(REG[12h], REG[11h], REG[10h]) REG[18h] bits [3:0]
Display
((REG[09h], REG[08h])+1) lines
Screen 1
Line 0 Line 1
Screen 1
(REG[15h], REG[14h], REG[13h]) REG[18h] bits [7:4] Line (REG[0Fh], REG[0Eh])
Screen 2 Screen 2
((REG[04h]+1)*8) pixels
(REG[17h], REG[16h])
Figure 10-3: Image Manipulation
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11 Clocking
11.1 Maximum MCLK: PCLK Ratios
Table 11-1: Maximum PCLK Frequency with EDO-DRAM Display type * Single Panel. * CRT. * Dual Monochrome/Color Panel with Half Frame Buffer Disabled. * Simultaneous CRT + Single Panel. * Simultaneous CRT + Dual Monochrome/Color Panel with Half Frame Buffer Disabled. * Dual Monochrome Panel with Half Frame Buffer Enabled. * Simultaneous CRT + Dual Monochrome Panel with Half Frame Buffer Enable. * Dual Color Panel with Half Frame Buffer Enabled. * Simultaneous CRT + Dual Color Panel with Half Frame Buffer Enable.
NRC
Maximum PCLK Allowed 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp
5, 4, 3
MCLK
5 4 3 5 4 3
MCLK/2 MCLK/2 MCLK MCLK/2 MCLK/2 MCLK/2
MCLK/2 MCLK/2 MCLK MCLK/2 MCLK/2 MCLK/2
MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/2
MCLK/2 MCLK/2 MCLK/2 MCLK/3 MCLK/2 MCLK/2
MCLK/3 MCLK/3 MCLK/2 MCLK/3 MCLK/3 MCLK/3
Table 11-2: Maximum PCLK Frequency with FPM-DRAM Display type * Single Panel. * CRT. * Dual Monochrome/Color Panel with Half Frame Buffer Disabled. * Simultaneous CRT + Single Panel. * Simultaneous CRT + Dual Monochrome/Color Panel with Half Frame Buffer Disabled. * Dual Monochrome Panel with Half Frame Buffer Enabled. * Simultaneous CRT + Dual Monochrome Panel with Half Frame Buffer Enable. * Dual Color Panel with Half Frame Buffer Enabled. * Simultaneous CRT + Dual Color Panel with Half Frame Buffer Enable.
NRC
Maximum PCLK allowed 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp
5, 4, 3
MCLK
5 4 3 5 4 3
MCLK/2 MCLK/2 MCLK MCLK/2 MCLK/2 MCLK/2
MCLK/2 MCLK/2 MCLK MCLK/2 MCLK/2 MCLK/2
MCLK/2 MCLK/2 MCLK MCLK/2 MCLK/2 MCLK/2
MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/2
MCLK/3 MCLK/2 MCLK/2 MCLK/3 MCLK/3 MCLK/2
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11.2 Frame Rate Calculation
The frame rate is calculated using the following formula:
PCLK max FrameRate = ---------------------------------------------------------------------------------------( HDP + HNDP ) x ( VDP + VNDP )
Where:
VDP VNDP HDP HNDP Ts = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = Pixel Clock = REG[09h] bits [1:0], REG[08h] bits [7:0] + 1 = REG[0Ah] bits [5:0] + 1 = in table below = ((REG[04h] bits [6:0]) + 1) * 8Ts = ((REG[05h] bits [4:0]) + 1) * 8Ts = given in table below = PCLK
Table 11-3: Example Frame Rates DRAM Type1 (Speed Grade) Color Depth (bpp) 1/2/4/8 16 1/2/4/8 16 1/2/4/8 16 1/2/4/8 16 1/2/4/8 16 1/2/4/8 16 1/2/4/8 16 20 13.3 20 13.3 40 Maximum Minimum Pixel Panel Clock HNDP(Ts) (MHz) 32 56 32 56 32 56 32 56 32 56 32 32 32 32 Maximum Frame Rate (Hz) Panel4 80 78 123 119 247 242 243 232 471 441 80 53 123 82 CRT 60 60 85 85 -
Display
Resolution
50ns
EDO-DRAM MClk = 40MHz NRC = 4 NRP = 1.5 NRCD = 2
* Single Panel. * CRT. * Dual Monochrome/Color Panel with Half Frame Buffer Disabled.5 * Simultaneous CRT + Single Panel. * Simultaneous CRT + Dual Monochrome/Color Panel with Half Frame Buffer Disabled.5
800x6002 640x480 640x240 480x320 320x240
* Dual Color with Half Frame Buffer Enabled. * Dual Mono with Half Frame Buffer Enabled.
800x6002,3 640x480
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Table 11-3: Example Frame Rates DRAM Type1 (Speed Grade) Color Depth (bpp) 1/2/4/8 16 1/2/4/8 16 1/2/4/8 16 1/2/4/8 16 1/2/4/8 16 1/2/4/8 16 1/2/4/8 16 1/2/4/8 16 1/2/4/8 16 1/2/4/8 16 1/2/4/8 16 1/2/4/8 16 1/2/4/8/16 1/2/4/8/16 1/2/4/8/16 1/2/4/8 16 1/2/4/8 16 12.5 12.5 12.5 12.5 8.33 12.5 8.33 25 16.5 11 16.5 11 33 Maximum Minimum Pixel Panel Clock HNDP(Ts) (MHz) 32 56 32 56 32 56 32 56 32 56 32 32 32 32 32 56 32 56 32 56 32 56 32 56 32 32 32 32 32 32 32 Maximum Frame Rate (Hz) Panel4 66 65 101 98 203 200 200 196 388 380 66 43 103 68 50 48 77 75 142 136 152 145 294 280 50 77 92 50 33 77 51 CRT 55 55 78 78 60 60 -
Display
Resolution
60ns
EDO-DRAM MClk = 33MHz NRC = 4 NRP = 1.5 NRCD = 2
* Single Panel. * CRT. * Dual Mono/Color Panel with Half Frame Buffer Disabled.5 * Simultaneous CRT + Single Panel. * Simultaneous CRT + Dual Mono/Color Panel with Half Frame Buffer Disabled.5
800x6002 640x480 640x240 480x320 320x240
* Dual Color with Half Frame Buffer Enabled. * Dual Mono with Half Frame Buffer Enabled. * Single Panel. * CRT. * Dual Mono/Color Panel with Half Frame Buffer Disabled.5 * Simultaneous CRT + Single Panel. * Simultaneous CRT + Dual Mono/Color Panel with Half Frame Buffer Disabled.5
800x6002,3 640x480 800x6002 640x480 640x240 480x320 320x240 800x6002 640x480 640x400
60ns
FPM-DRAM
MClk = 25MHz NRC = 4 NRP = 1.5 * Dual Mono with Half Frame Buffer NRCD = 2 Enabled.
* Dual Color with Half Frame Buffer Enabled.
800x6002,3 640x480
1. 2. 3. 4. 5.
Must set NRC = 4MCLK. See REG[22h], "Performance Enhancement Register 0". 800x600 @ 16 bpp requires 2M bytes of display buffer for all display types. 800x600 @ 8 bpp on a dual color panel requires 2M bytes of display buffer if the half frame buffer is enabled. Optimum frame rates for panels range from 60Hz to 150Hz. If the maximum refresh rate is too high for a panel, MCLK should be reduced or PCLK should be divided down. Half Frame Buffer disabled by REG[1Bh] bit 0.
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12 Look-Up Table Architecture
Table 12-1: Look-Up Table Configurations Display Mode RED Black & White 4-level gray 16-level gray 2 color 4 color 16 color 256 color 1 bank of 2 entries 4 banks of 4 entries 1 bank of 16 entries 2 banks of 8 entries 4-Bit Wide Look-Up Table GREEN 1 bank of 2 entries 4 banks of 4 entries 1 bank of 16 entries 1 bank of 2 entries 4 banks of 4 entries 1 bank of 16 entries 2 banks of 8 entries 1 bank of 2 entries 4 banks of 4 entries 1 bank of 16 entries 4 banks of 4 entries BLUE
Indicates the look-up table is not used for that display mode
The following depictions are intended to show the display data output path only. The CPU R/W access to the individual Look-Up Tables is not affected by the various "banking" configurations.
12.1 Gray Shade Display Modes
1 Bit-Per-Pixel Mode
Green Look-Up Table
0 1 1-bit pixel data Entry 0 1 Select Logic 4-bit display data output
Figure 12-1: 1 Bit-Per-Pixel - 2-Level Gray-Shade Mode Look-Up Table Architecture
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2 Bit-Per-Pixel Mode
Green Look-Up Table Bank 0 0 1 2 3 Bank 1 4 5 6 7 Bank 2 8 9 A B Bank 3 C D E F Bank Select bits [1:0] REG[27h] bits [1:0] 2-bit pixel data
00
01 Bank Select Logic 10
Selected Bank 00 Entry 01 Select 4-bit display data output 10 11 Logic
11
Note: the above depiction is intended to show the display data output path only. The CPU R/W access to the individual Look-Up Tables is not affected by the various "banking" configurations.
Figure 12-2: 2 Bit-Per-Pixel - 4-Level Gray-Shade Mode Look-Up Table Architecture
4 Bit-Per-Pixel Mode
Green Look-Up Table 0 1 2 3 4 5 6 7 8 9 A B C D E F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Entry Select Logic
4-bit display data output
4-bit pixel data
Figure 12-3: 4 Bit-Per-Pixel - 16-Level Gray-Shade Mode Look-Up Table Architecture
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12.2 Color Display Modes
1 Bit-Per-Pixel Color Mode
Red Look-Up Table
0 1 1-bit pixel data 0 Entry 1 Select Logic 4-bit Red data output
Green Look-Up Table
0 1 0 Entry 1 Select Logic 4-bit Green data output
Blue Look-Up Table
0 1 0 Entry 1 Select Logic 4-bit Blue data output
Figure 12-4: 1 Bit-Per-Pixel - 2-Level Color Look-Up Table Architecture
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2 Bit-Per-Pixel Color Mode
Red Look-Up Table
Bank 0 0 1 2 3 Bank 1 4 5 6 7 Bank 2 8 9 A B Bank 3 C D E F Bank Select bits [1:0] REG[27h] bits [5:4] 11 01 Bank Select Logic 10 Selected Bank 00 Entry 01 Select 10 11 Logic 4-bit Red data output 00
2-bit pixel data
Green Look-Up Table
Bank 0 0 1 2 3 Bank 1 4 5 6 7 Bank 2 8 9 A B Bank 3 C D E F Bank Select bits [1:0] REG[27h] bits [1:0] 11 01 Bank Select Logic 10 Selected Bank 00 Entry 01 Select 10 11 Logic 4-bit Green data output 00
Blue Look-Up Table
Bank 0 0 1 2 3 Bank 1 4 5 6 7 Bank 2 8 9 A B Bank 3 C D E F Bank Select bits [1:0] REG[27h] bits [3:2] 11 01 Bank Select Logic 10 Selected Bank 00 Entry 01 Select 10 11 Logic 4-bit Blue data output 00
Figure 12-5: 2 Bit-Per-Pixel - 4-Level Color Mode Look-Up Table Architecture
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4 Bit-Per-Pixel Color Mode
Red Look-Up Table 0 1 2 3 4 5 6 7 8 9 A B C D E F 4-bit pixel data 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Entry Select Logic
4-bit Red data output
Green Look-Up Table 0 1 2 3 4 5 6 7 8 9 A B C D E F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Entry Select Logic
4-bit Green data output
Blue Look-Up Table 0 1 2 3 4 5 6 7 8 9 A B C D E F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Entry Select Logic
4-bit Blue data output
Figure 12-6: 4 Bit-Per-Pixel - 16-Level Color Mode Look-Up Table Architecture
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8 Bit-Per-Pixel Color Mode
256 Color Data Format: 7 6 5 4 3 2 1 0
Bank 0 0 1 2 3 4 5 6 7 Bank 1 8 9 A B C D E F Bank Select bit REG[27h] bit 4 3-bit pixel data
Red Look-Up Table
R2 R1 R0 G2 G1 G0 B1 B0
0
Selected Bank 000 001 010 Entry 011 Select 4-bit Red data output 100 101 Logic 110 111
Bank Select Logic 1
Green Look-Up Table
Bank 0 0 1 2 3 4 5 6 7 Bank 1 8 9 A B C D E F Bank Select bit REG[27h] bit 0 3-bit pixel data
0
Selected Bank 000 001 010 Entry 011 Select 4-bit Green data output 100 101 Logic 110 111
Bank Select Logic 1
Blue Look-Up Table
Bank 0 0 1 2 3 Bank 1 4 5 6 7 Bank 2 8 9 A B Bank 3 C D E F Bank Select bits [1:0] REG[27h] bits [3:2] 11 01 Bank Select Logic 10 Selected Bank 00 Entry 01 Select 10 11 Logic 4-bit Blue data output 00
2-bit pixel data
Figure 12-7: 8 Bit-Per-Pixel - 256-Level Color Mode Look-Up Table Architecture
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13 Power Save Modes
Two Power Save Modes have been incorporated into the S1D13504 to accommodate the important need for power reduction in the hand-held devices market. These modes are hardware suspend and software suspend.
13.1 Hardware Suspend
* Register read/write disallowed. * Memory read/write disallowed. * LCD outputs are forced low (see Note 1 of Section 13.4, "Pin States in Power Save Modes" on page 128). * LCDPWR forced to Off state. * CRT outputs are disabled. * If suspend mode CBR refresh is selected, all internal modules and clocks except the Memory I/F are shut down. * If suspend mode self-refresh or no-refresh is selected, all internal modules and clocks are shut down.
13.2 Software Suspend
* Register read/write allowed except for RAMDAC registers. * Memory read/write disallowed. * LCD outputs are forced low (see Note 1 of Section 13.4, "Pin States in Power Save Modes" on page 128). * LCDPWR forced to Off state. * CRT outputs are disabled. * If suspend mode CBR refresh is selected, all internal modules and clocks except the Host Bus I/F and the Memory I/F are shut down. * If suspend mode self-refresh or no-refresh is selected, all internal modules and clocks except the Host Bus I/F are shut down.
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13.3 Power Save Mode Function Summary
Table 13-1: Power Save Mode Function Summary Power Save Mode (PSM) Function Display Active? Register Access Possible? Memory Access Possible? Host Bus Interface Running? Memory Interface Running? Yes Yes Yes Yes Yes Normal (Active) No Yes (1) No Yes No (2) Software Suspend No No No No No (2) Hardware Suspend
Note (1) except for RAMDAC registers. (2) Yes if CBR suspend mode refresh is selected.
13.4 Pin States in Power Save Modes
Table 13-2: Pin States in Power Save Modes Pin State Pins LCD outputs LCDPWR DRAM outputs CRT / DAC outputs Host Interface outputs Normal (Active) Active On Active Active Active Software Suspend Forced Low (1) Off Refresh Only (2) Disabled (3) Active (4) Hardware Suspend Forced Low (1) Off Refresh Only (2) Disabled (3) Disabled
Note 1. FPFRAME and FPLINE are forced to their inactive states as defined by REG[0Ch] bit 6 and REG[07h] bit 6 respectively. 2. Selectable: may be CBR refresh, self-refresh or no refresh at all. 3. DACWR#, DACRD#, DACRS0, DACRS1 are active but DACCLK is disabled. 4. Active for non-DAC register access only.
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14 Mechanical Data
14.1 QFP15-128 (S1D13504F00A)
QFP15 - 128 pin Unit: mm
16.0 0.4 14.0 0.1 96 65
97
64
Index
128
33
1 0.125 0.1 0.4 1.4 0.1 0.16 0.1
32
14.0 0.1 0.1 0.5 0.2 1.0
Figure 14-1: Mechanical Drawing QFP15-128
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16.0 0.4 0~10
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14.2 TQFP15-128 (S1D13504F01A)
TQFP15 - 128 pin Unit: mm
16 14
96
0.4 0.1
65
97
64
0.1
14
INDEX 128 33 1 32
0.4
0.1
0.16
+0.05 - 0.03
1.2 max
0.125
+0.05 - 0.025
1
0.1
0 10 0.5 1
0.2
Figure 14-2: Mechanical Drawing TQFP15-128
S1D13504 X19A-A-002-19
16
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14.3 QFP20-144 (S1D13504F02A)
QFP20 - 144 pin Unit: mm
22 20
108 109
0.4 0.1
73 72
0.1
20
INDEX 144 1 36 37
0.5
0.2
+0.1 - 0.05
1.4
0.1
1.7 max
0.125
+0.05 - 0.025
0.1
0 10 0.5 1
0.2
Figure 14-3: Mechanical Drawing QFP20-144
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22
0.4
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15 References
The following documents contain additional information related to the S1D13504. Document numbers are listed in parenthesis after the document name. All documents can be found at the Epson Research and Development Website at www.erd.epson.com. * S1D13504 Product Brief (X19A-C-002-xx) * S1D13504 Windows CE v2.x Display Drivers (X19A-E-001-xx) * S1D13504 Wind River WindML v2.0 Display Drivers (X19A-E-002-xx) * S1D13504 Wind River UGL v1.2 Display Drivers (X19A-E-003-xx) * S1D13504 Programming Notes And Examples (X19A-G-002-xx) * S5U13504B00C Evaluation Board User Manual (X19A-G-004-xx) * Interfacing to the Philips MIPS PR31500/PR31700 Microprocessor (X19A-G-005-xx) * S1D13504 Power Consumption (X19A-G-006-xx) * Interfacing to the NEC VR4102 Microprocessors (X19A-G-007-xx) * Interfacing to the ODO Display Card Interface (X19A-G-008-xx) * Interfacing to the PC Card Bus (X19A-G-009-xx) * Interfacing to the Motorola MPC821 Microprocessor (X19A-G-010-xx) * Interfacing to the Motorola MCF5307 "Coldfire" Microprocessors (X19A-G-011-xx) * Interfacing to the Toshiba TX3912 Microprocessor (X19A-G-012-xx) * Interfacing to the Motorola MC68328 "Dragonball" Microprocessor (X19A-G-013-xx) * S1D13504 Register Summary (X19A-Q-001-xx)
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16 Sales and Technical Support
Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp/ North America Epson Electronics America, Inc. 150 River Oaks Parkway San Jose, CA 95134, USA Tel: (408) 922-0200 Fax: (408) 922-0238 http://www.eea.epson.com/ Taiwan Epson Taiwan Technology & Trading Ltd. 10F, No. 287 Nanking East Road Sec. 3, Taipei, Taiwan Tel: 02-2717-7360 Fax: 02-2712-9164 http://www.epson.com.tw/ Singapore Epson Singapore Pte., Ltd. No. 1 Temasek Avenue #36-00 Millenia Tower Singapore, 039192 Tel: 337-7911 Fax: 334-2716 http://www.epson.com.sg/
Hong Kong Epson Hong Kong Ltd. 20/F., Harbour Centre 25 Harbour Road Wanchai, Hong Kong Tel: 2585-4600 Fax: 2827-4346 http://www.epson.com.hk/
Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich, Germany Tel: 089-14005-0 Fax: 089-14005-110 http://www.epson-electronics.de/
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